| Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 1 | /* |
| Madhukar Pappireddy | fc9b411 | 2019-12-23 14:49:52 -0600 | [diff] [blame] | 2 | * Copyright (c) 2019-2020, Intel Corporation. All rights reserved. |
| Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SOCFPGA_SYSTEMMANAGER_H |
| 8 | #define SOCFPGA_SYSTEMMANAGER_H |
| 9 | |
| 10 | #include "socfpga_plat_def.h" |
| 11 | |
| 12 | /* System Manager Register Map */ |
| 13 | |
| 14 | #define SOCFPGA_SYSMGR_SDMMC 0x28 |
| 15 | |
| 16 | #define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0 |
| 17 | #define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4 |
| 18 | #define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8 |
| 19 | #define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc |
| 20 | #define SOCFPGA_SYSMGR_NOC_IDLEACK 0xd0 |
| 21 | #define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xd4 |
| 22 | |
| 23 | #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200 |
| 24 | #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204 |
| 25 | #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208 |
| 26 | |
| 27 | /* Field Masking */ |
| 28 | |
| 29 | #define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) |
| 30 | |
| 31 | #define IDLE_DATA_LWSOC2FPGA BIT(0) |
| 32 | #define IDLE_DATA_SOC2FPGA BIT(4) |
| 33 | #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) |
| 34 | |
| 35 | #define SCR_AXI_AP_MASK BIT(24) |
| 36 | #define SCR_FPGA2SOC_MASK BIT(16) |
| 37 | #define SCR_MPU_MASK BIT(0) |
| 38 | #define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \ |
| 39 | | SCR_MPU_MASK) |
| 40 | #define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 |
| 41 | |
| 42 | /* Macros */ |
| 43 | |
| 44 | #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ |
| 45 | + (SOCFPGA_SYSMGR_##_reg)) |
| 46 | |
| 47 | #define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \ |
| 48 | + (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg)) |
| 49 | |
| 50 | #define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \ |
| 51 | + (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg)) |
| 52 | |
| 53 | /* L3 Interconnect Register Map */ |
| 54 | #define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000 |
| 55 | #define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004 |
| 56 | #define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c |
| 57 | #define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010 |
| 58 | #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c |
| 59 | #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020 |
| 60 | #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024 |
| 61 | #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028 |
| 62 | #define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c |
| 63 | #define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030 |
| 64 | #define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034 |
| 65 | #define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040 |
| 66 | #define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044 |
| 67 | #define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048 |
| 68 | #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050 |
| 69 | #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054 |
| 70 | #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058 |
| 71 | #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c |
| 72 | #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060 |
| 73 | #define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064 |
| 74 | #define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068 |
| 75 | #define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c |
| 76 | #define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070 |
| 77 | |
| 78 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008 |
| 79 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c |
| 80 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010 |
| 81 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014 |
| 82 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018 |
| 83 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c |
| 84 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020 |
| 85 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c |
| 86 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030 |
| 87 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034 |
| 88 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038 |
| 89 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040 |
| 90 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044 |
| 91 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048 |
| 92 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c |
| 93 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054 |
| 94 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058 |
| 95 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c |
| 96 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060 |
| 97 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064 |
| 98 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068 |
| 99 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c |
| 100 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070 |
| 101 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074 |
| 102 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078 |
| 103 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090 |
| 104 | #define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094 |
| 105 | |
| 106 | #define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 |
| 107 | #define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 |
| 108 | |
| Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 109 | void enable_ns_peripheral_access(void); |
| 110 | void enable_ns_bridge_access(void); |
| 111 | |
| 112 | #endif /* SOCFPGA_SYSTEMMANAGER_H */ |