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Jens Wiklander52c798e2015-12-07 14:37:10 +01001/*
2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Jens Wiklander52c798e2015-12-07 14:37:10 +01005 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <assert.h>
10#include <bl_common.h>
Jens Wiklander52c798e2015-12-07 14:37:10 +010011#include <platform_def.h>
12#include "qemu_private.h"
13
Jens Wiklander52c798e2015-12-07 14:37:10 +010014/* Data structure which holds the extents of the trusted SRAM for BL1*/
15static meminfo_t bl1_tzram_layout;
16
17
18meminfo_t *bl1_plat_sec_mem_layout(void)
19{
20 return &bl1_tzram_layout;
21}
22
23/*******************************************************************************
24 * Perform any BL1 specific platform actions.
25 ******************************************************************************/
26void bl1_early_platform_setup(void)
27{
Jens Wiklander52c798e2015-12-07 14:37:10 +010028 /* Initialize the console to provide early debug support */
Michalis Pappascca6cb72018-03-04 15:43:38 +080029 qemu_console_init();
Jens Wiklander52c798e2015-12-07 14:37:10 +010030
31 /* Allow BL1 to see the whole Trusted RAM */
32 bl1_tzram_layout.total_base = BL_RAM_BASE;
33 bl1_tzram_layout.total_size = BL_RAM_SIZE;
Jens Wiklander52c798e2015-12-07 14:37:10 +010034}
35
36/******************************************************************************
37 * Perform the very early platform specific architecture setup. This only
38 * does basic initialization. Later architectural setup (bl1_arch_setup())
39 * does not do anything platform specific.
40 *****************************************************************************/
Etienne Carriere911de8c2018-02-02 13:23:22 +010041#ifdef AARCH32
Antonio Nino Diaz099b0b12018-09-26 09:29:45 +010042#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
Etienne Carriere911de8c2018-02-02 13:23:22 +010043#else
44#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_el3(__VA_ARGS__)
45#endif
46
Jens Wiklander52c798e2015-12-07 14:37:10 +010047void bl1_plat_arch_setup(void)
48{
Etienne Carriere911de8c2018-02-02 13:23:22 +010049 QEMU_CONFIGURE_BL1_MMU(bl1_tzram_layout.total_base,
Jens Wiklander52c798e2015-12-07 14:37:10 +010050 bl1_tzram_layout.total_size,
Michalis Pappasba861122018-02-28 14:36:03 +080051 BL_CODE_BASE, BL1_CODE_END,
52 BL1_RO_DATA_BASE, BL1_RO_DATA_END,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +090053 BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
Jens Wiklander52c798e2015-12-07 14:37:10 +010054}
55
56void bl1_platform_setup(void)
57{
58 plat_qemu_io_setup();
59}