Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <assert.h> |
| 32 | #include <console.h> |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 33 | #include <debug.h> |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 34 | #include <mmio.h> |
| 35 | #include <plat_arm.h> |
| 36 | #include <platform.h> |
| 37 | #include <platform_def.h> |
| 38 | #include <platform_sp_min.h> |
| 39 | |
| 40 | #define BL32_END (uintptr_t)(&__BL32_END__) |
| 41 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 42 | static entry_point_info_t bl33_image_ep_info; |
| 43 | |
| 44 | /* Weak definitions may be overridden in specific ARM standard platform */ |
| 45 | #pragma weak sp_min_early_platform_setup |
| 46 | #pragma weak sp_min_platform_setup |
| 47 | #pragma weak sp_min_plat_arch_setup |
| 48 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 49 | |
| 50 | /******************************************************************************* |
| 51 | * Return a pointer to the 'entry_point_info' structure of the next image for the |
| 52 | * security state specified. BL33 corresponds to the non-secure image type |
| 53 | * while BL32 corresponds to the secure image type. A NULL pointer is returned |
| 54 | * if the image does not exist. |
| 55 | ******************************************************************************/ |
| 56 | entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) |
| 57 | { |
| 58 | entry_point_info_t *next_image_info; |
| 59 | |
| 60 | next_image_info = &bl33_image_ep_info; |
| 61 | |
| 62 | /* |
| 63 | * None of the images on the ARM development platforms can have 0x0 |
| 64 | * as the entrypoint |
| 65 | */ |
| 66 | if (next_image_info->pc) |
| 67 | return next_image_info; |
| 68 | else |
| 69 | return NULL; |
| 70 | } |
| 71 | |
| 72 | /******************************************************************************* |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 73 | * Perform early platform setup. |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 74 | ******************************************************************************/ |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 75 | void arm_sp_min_early_platform_setup(void *from_bl2, |
| 76 | void *plat_params_from_bl2) |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 77 | { |
| 78 | /* Initialize the console to provide early debug support */ |
| 79 | console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, |
| 80 | ARM_CONSOLE_BAUDRATE); |
| 81 | |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 82 | #if RESET_TO_SP_MIN |
| 83 | /* There are no parameters from BL2 if SP_MIN is a reset vector */ |
| 84 | assert(from_bl2 == NULL); |
| 85 | assert(plat_params_from_bl2 == NULL); |
| 86 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 87 | /* Populate entry point information for BL33 */ |
| 88 | SET_PARAM_HEAD(&bl33_image_ep_info, |
| 89 | PARAM_EP, |
| 90 | VERSION_1, |
| 91 | 0); |
| 92 | /* |
| 93 | * Tell SP_MIN where the non-trusted software image |
| 94 | * is located and the entry state information |
| 95 | */ |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 96 | bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 97 | bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); |
| 98 | SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 99 | |
| 100 | #else /* RESET_TO_SP_MIN */ |
| 101 | |
| 102 | /* |
| 103 | * Check params passed from BL2 should not be NULL, |
| 104 | */ |
| 105 | bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; |
| 106 | assert(params_from_bl2 != NULL); |
| 107 | assert(params_from_bl2->h.type == PARAM_BL_PARAMS); |
| 108 | assert(params_from_bl2->h.version >= VERSION_2); |
| 109 | |
| 110 | bl_params_node_t *bl_params = params_from_bl2->head; |
| 111 | |
| 112 | /* |
| 113 | * Copy BL33 entry point information. |
| 114 | * They are stored in Secure RAM, in BL2's address space. |
| 115 | */ |
| 116 | while (bl_params) { |
| 117 | if (bl_params->image_id == BL33_IMAGE_ID) { |
| 118 | bl33_image_ep_info = *bl_params->ep_info; |
| 119 | break; |
| 120 | } |
| 121 | |
| 122 | bl_params = bl_params->next_params_info; |
| 123 | } |
| 124 | |
| 125 | if (bl33_image_ep_info.pc == 0) |
| 126 | panic(); |
| 127 | |
| 128 | #endif /* RESET_TO_SP_MIN */ |
| 129 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 130 | } |
| 131 | |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 132 | void sp_min_early_platform_setup(void *from_bl2, |
| 133 | void *plat_params_from_bl2) |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 134 | { |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 135 | arm_sp_min_early_platform_setup(from_bl2, plat_params_from_bl2); |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 136 | |
| 137 | /* |
| 138 | * Initialize Interconnect for this cluster during cold boot. |
| 139 | * No need for locks as no other CPU is active. |
| 140 | */ |
| 141 | plat_arm_interconnect_init(); |
| 142 | |
| 143 | /* |
| 144 | * Enable Interconnect coherency for the primary CPU's cluster. |
| 145 | * Earlier bootloader stages might already do this (e.g. Trusted |
| 146 | * Firmware's BL1 does it) but we can't assume so. There is no harm in |
| 147 | * executing this code twice anyway. |
| 148 | * Platform specific PSCI code will enable coherency for other |
| 149 | * clusters. |
| 150 | */ |
| 151 | plat_arm_interconnect_enter_coherency(); |
| 152 | } |
| 153 | |
| 154 | /******************************************************************************* |
| 155 | * Perform platform specific setup for SP_MIN |
| 156 | ******************************************************************************/ |
| 157 | void sp_min_platform_setup(void) |
| 158 | { |
| 159 | /* Initialize the GIC driver, cpu and distributor interfaces */ |
| 160 | plat_arm_gic_driver_init(); |
| 161 | plat_arm_gic_init(); |
| 162 | |
| 163 | /* |
| 164 | * Do initial security configuration to allow DRAM/device access |
| 165 | * (if earlier BL has not already done so). |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 166 | */ |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 167 | #if RESET_TO_SP_MIN |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 168 | plat_arm_security_setup(); |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 169 | #endif |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 170 | |
| 171 | /* Enable and initialize the System level generic timer */ |
| 172 | mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, |
| 173 | CNTCR_FCREQ(0) | CNTCR_EN); |
| 174 | |
| 175 | /* Allow access to the System counter timer module */ |
| 176 | arm_configure_sys_timer(); |
| 177 | |
| 178 | /* Initialize power controller before setting up topology */ |
| 179 | plat_arm_pwrc_setup(); |
| 180 | } |
| 181 | |
| 182 | /******************************************************************************* |
| 183 | * Perform the very early platform specific architectural setup here. At the |
| 184 | * moment this only initializes the MMU |
| 185 | ******************************************************************************/ |
| 186 | void sp_min_plat_arch_setup(void) |
| 187 | { |
| 188 | |
| 189 | arm_setup_page_tables(BL32_BASE, |
| 190 | (BL32_END - BL32_BASE), |
| 191 | BL_CODE_BASE, |
Masahiro Yamada | 51bef61 | 2017-01-18 02:10:08 +0900 | [diff] [blame] | 192 | BL_CODE_END, |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 193 | BL_RO_DATA_BASE, |
Masahiro Yamada | 51bef61 | 2017-01-18 02:10:08 +0900 | [diff] [blame] | 194 | BL_RO_DATA_END |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 195 | #if USE_COHERENT_MEM |
Masahiro Yamada | 0fac5af | 2016-12-28 16:11:41 +0900 | [diff] [blame] | 196 | , BL_COHERENT_RAM_BASE, |
| 197 | BL_COHERENT_RAM_END |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 198 | #endif |
| 199 | ); |
| 200 | |
| 201 | enable_mmu_secure(0); |
| 202 | } |