Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Summer Qin | 93c812f | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 8 | #include <plat_arm.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 9 | #include <platform_def.h> |
| 10 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 11 | /******************************************************************************* |
| 12 | * This function validates an MPIDR by checking whether it falls within the |
| 13 | * acceptable bounds. An error code (-1) is returned if an incorrect mpidr |
| 14 | * is passed. |
| 15 | ******************************************************************************/ |
| 16 | int arm_check_mpidr(u_register_t mpidr) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 17 | { |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 18 | unsigned int cluster_id, cpu_id; |
Summer Qin | 93c812f | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 19 | uint64_t valid_mask; |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 20 | |
Summer Qin | 93c812f | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 21 | #if ARM_PLAT_MT |
| 22 | unsigned int pe_id; |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 23 | |
Summer Qin | 93c812f | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 24 | valid_mask = ~(MPIDR_AFFLVL_MASK | |
| 25 | (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | |
| 26 | (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)); |
| 27 | cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; |
| 28 | cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; |
| 29 | pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; |
| 30 | #else |
| 31 | valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK); |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 32 | cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; |
| 33 | cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; |
Summer Qin | 93c812f | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 34 | #endif /* ARM_PLAT_MT */ |
| 35 | |
| 36 | mpidr &= MPIDR_AFFINITY_MASK; |
| 37 | if (mpidr & valid_mask) |
| 38 | return -1; |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 39 | |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 40 | if (cluster_id >= PLAT_ARM_CLUSTER_COUNT) |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 41 | return -1; |
| 42 | |
| 43 | /* Validate cpu_id by checking whether it represents a CPU in |
| 44 | one of the two clusters present on the platform. */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 45 | if (cpu_id >= plat_arm_get_cluster_core_count(mpidr)) |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 46 | return -1; |
| 47 | |
Summer Qin | 93c812f | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 48 | #if ARM_PLAT_MT |
| 49 | if (pe_id >= plat_arm_get_cpu_pe_count(mpidr)) |
| 50 | return -1; |
| 51 | #endif /* ARM_PLAT_MT */ |
| 52 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 53 | return 0; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 54 | } |