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git01.mediatek.com / filogic / atf / 26c04791fa1d02d253abf377bd2050188361fdbc / . / plat / mediatek / mt8196 / drivers / gpio / mtgpio.c
blob: a34f706a933638404f0ef7f5e99bbc7ac8f7ab8e [file] [log] [blame]
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]1/*
2 * Copyright (c) 2024, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <platform_def.h>
9#include <mtgpio.h>
10
11typedef enum {
12 REG_0 = 0,
13 REG_1,
14 REG_2,
15 REG_3,
16 REG_4,
17 REG_5,
18 REG_6,
19 REG_7,
20 REG_8,
21 REG_9,
22 REG_10,
23 REG_11,
24 REG_12,
25 REG_13,
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]26 REG_14,
27 REG_15
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]28} RegEnum;
29
30uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
31{
32 uintptr_t reg_addr = 0U;
33 struct mt_pin_info gpio_info;
34
35 assert(pin < MAX_GPIO_PIN);
36
37 gpio_info = mt_pin_infos[pin];
38
39 switch (gpio_info.base & 0xF) {
40 case REG_0:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]41 reg_addr = GPIO_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]42 break;
43 case REG_1:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]44 reg_addr = IOCFG_RT_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]45 break;
46 case REG_2:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]47 reg_addr = IOCFG_RM1_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]48 break;
49 case REG_3:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]50 reg_addr = IOCFG_RM2_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]51 break;
52 case REG_4:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]53 reg_addr = IOCFG_RB_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]54 break;
55 case REG_5:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]56 reg_addr = IOCFG_BM1_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]57 break;
58 case REG_6:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]59 reg_addr = IOCFG_BM2_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]60 break;
61 case REG_7:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]62 reg_addr = IOCFG_BM3_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]63 break;
64 case REG_8:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]65 reg_addr = IOCFG_LT_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]66 break;
67 case REG_9:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]68 reg_addr = IOCFG_LM1_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]69 break;
70 case REG_10:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]71 reg_addr = IOCFG_LM2_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]72 break;
73 case REG_11:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]74 reg_addr = IOCFG_LB1_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]75 break;
76 case REG_12:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]77 reg_addr = IOCFG_LB2_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]78 break;
79 case REG_13:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]80 reg_addr = IOCFG_TM1_BASE;
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]81 break;
82 case REG_14:
developerf2098942025-02-25 16:42:41 +0800[diff] [blame]83 reg_addr = IOCFG_TM2_BASE;
84 break;
85 case REG_15:
developerfcbc2022024-02-27 17:07:31 +0800[diff] [blame]86 reg_addr = IOCFG_TM3_BASE;
87 break;
88 default:
89 break;
90 }
91
92 return reg_addr;
93}