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Caesar Wanga8456902016-10-27 01:12:34 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Caesar Wanga8456902016-10-27 01:12:34 +08005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef DFS_H
8#define DFS_H
Caesar Wanga8456902016-10-27 01:12:34 +08009
Paul Kocialkowskie0f2c3b2018-06-13 20:37:25 +020010#include <stdint.h>
11
Caesar Wanga8456902016-10-27 01:12:34 +080012struct rk3399_sdram_default_config {
13 unsigned char bl;
14 /* 1:auto precharge, 0:never auto precharge */
15 unsigned char ap;
16 /* dram driver strength */
17 unsigned char dramds;
18 /* dram ODT, if odt=0, this parameter invalid */
19 unsigned char dramodt;
20 /* ca ODT, if odt=0, this parameter invalid
21 * only used by LPDDR4
22 */
23 unsigned char caodt;
24 unsigned char burst_ref_cnt;
25 /* zqcs period, unit(s) */
26 unsigned char zqcsi;
27};
28
Caesar Wanga8456902016-10-27 01:12:34 +080029struct drv_odt_lp_config {
Caesar Wanga8456902016-10-27 01:12:34 +080030 uint32_t pd_idle;
31 uint32_t sr_idle;
32 uint32_t sr_mc_gate_idle;
33 uint32_t srpd_lite_idle;
34 uint32_t standby_idle;
Derek Basehoreff461d02016-10-20 20:46:43 -070035 uint32_t odt_en;
Caesar Wanga8456902016-10-27 01:12:34 +080036
37 uint32_t dram_side_drv;
38 uint32_t dram_side_dq_odt;
39 uint32_t dram_side_ca_odt;
Caesar Wanga8456902016-10-27 01:12:34 +080040};
41
Caesar Wanga8456902016-10-27 01:12:34 +080042uint32_t ddr_set_rate(uint32_t hz);
43uint32_t ddr_round_rate(uint32_t hz);
44uint32_t ddr_get_rate(void);
Derek Basehoreff461d02016-10-20 20:46:43 -070045uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2);
46void dram_dfs_init(void);
Derek Basehoree13bc542017-02-24 14:31:36 +080047void ddr_prepare_for_sys_suspend(void);
48void ddr_prepare_for_sys_resume(void);
49
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000050#endif /* DFS_H */