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Douglas Raillardd7c21b72017-06-28 15:23:03 +01001ARM Trusted Firmware User Guide
2===============================
3
4
5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
10This document describes how to build ARM Trusted Firmware (TF) and run it with a
11tested set of other software components using defined configurations on the Juno
12ARM development platform and ARM Fixed Virtual Platform (FVP) models. It is
13possible to use other software components, configurations and platforms but that
14is outside the scope of this document.
15
16This document assumes that the reader has previous experience running a fully
17bootable Linux software stack on Juno or FVP using the prebuilt binaries and
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010018filesystems provided by `Linaro`_. Further information may be found in the
19`Linaro instructions`_. It also assumes that the user understands the role of
20the different software components required to boot a Linux system:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
22- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
23- Normal world bootloader (e.g. UEFI or U-Boot)
24- Device tree
25- Linux kernel image
26- Root filesystem
27
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010028This document also assumes that the user is familiar with the `FVP models`_ and
Douglas Raillardd7c21b72017-06-28 15:23:03 +010029the different command line options available to launch the model.
30
31This document should be used in conjunction with the `Firmware Design`_.
32
33Host machine requirements
34-------------------------
35
36The minimum recommended machine specification for building the software and
37running the FVP models is a dual-core processor running at 2GHz with 12GB of
38RAM. For best performance, use a machine with a quad-core processor running at
392.6GHz with 16GB of RAM.
40
41The software has been tested on Ubuntu 14.04 LTS (64-bit). Packages used for
42building the software were installed from that distribution unless otherwise
43specified.
44
45The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
David Cunadob2de0992017-06-29 12:01:33 +010046Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010047
48Tools
49-----
50
51Install the required packages to build Trusted Firmware with the following
52command:
53
54::
55
56 sudo apt-get install build-essential gcc make git libssl-dev
57
David Cunado82509be2017-12-19 16:33:25 +000058ARM TF has been tested with `Linaro Release 17.10`_.
David Cunadob2de0992017-06-29 12:01:33 +010059
Douglas Raillardd7c21b72017-06-28 15:23:03 +010060Download and install the AArch32 or AArch64 little-endian GCC cross compiler.
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010061The `Linaro Release Notes`_ documents which version of the compiler to use for a
62given Linaro Release. Also, these `Linaro instructions`_ provide further
63guidance and a script, which can be used to download Linaro deliverables
64automatically.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010065
66Optionally, Trusted Firmware can be built using clang or ARM Compiler 6.
67See instructions below on how to switch the default compiler.
68
69In addition, the following optional packages and tools may be needed:
70
71- ``device-tree-compiler`` package if you need to rebuild the Flattened Device
72 Tree (FDT) source files (``.dts`` files) provided with this software.
73
74- For debugging, ARM `Development Studio 5 (DS-5)`_.
75
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010076- To create and modify the diagram files included in the documentation, `Dia`_.
77 This tool can be found in most Linux distributions. Inkscape is needed to
78 generate the actual *.png files.
79
Douglas Raillardd7c21b72017-06-28 15:23:03 +010080Getting the Trusted Firmware source code
81----------------------------------------
82
83Download the Trusted Firmware source code from Github:
84
85::
86
87 git clone https://github.com/ARM-software/arm-trusted-firmware.git
88
89Building the Trusted Firmware
90-----------------------------
91
92- Before building Trusted Firmware, the environment variable ``CROSS_COMPILE``
93 must point to the Linaro cross compiler.
94
95 For AArch64:
96
97 ::
98
99 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
100
101 For AArch32:
102
103 ::
104
105 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
106
107 It is possible to build Trusted Firmware using clang or ARM Compiler 6.
108 To do so ``CC`` needs to point to the clang or armclang binary. Only the
109 compiler is switched; the assembler and linker need to be provided by
110 the GNU toolchain, thus ``CROSS_COMPILE`` should be set as described above.
111
112 ARM Compiler 6 will be selected when the base name of the path assigned
113 to ``CC`` matches the string 'armclang'.
114
115 For AArch64 using ARM Compiler 6:
116
117 ::
118
119 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
120 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
121
122 Clang will be selected when the base name of the path assigned to ``CC``
123 contains the string 'clang'. This is to allow both clang and clang-X.Y
124 to work.
125
126 For AArch64 using clang:
127
128 ::
129
130 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
131 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
132
133- Change to the root directory of the Trusted Firmware source tree and build.
134
135 For AArch64:
136
137 ::
138
139 make PLAT=<platform> all
140
141 For AArch32:
142
143 ::
144
145 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
146
147 Notes:
148
149 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
150 `Summary of build options`_ for more information on available build
151 options.
152
153 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
154
155 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
156 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is
157 provided by ARM Trusted Firmware to demonstrate how PSCI Library can
158 be integrated with an AArch32 EL3 Runtime Software. Some AArch32 EL3
159 Runtime Software may include other runtime services, for example
160 Trusted OS services. A guide to integrate PSCI library with AArch32
161 EL3 Runtime Software can be found `here`_.
162
163 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
164 image, is not compiled in by default. Refer to the
165 `Building the Test Secure Payload`_ section below.
166
167 - By default this produces a release version of the build. To produce a
168 debug version instead, refer to the "Debugging options" section below.
169
170 - The build process creates products in a ``build`` directory tree, building
171 the objects and binaries for each boot loader stage in separate
172 sub-directories. The following boot loader binary files are created
173 from the corresponding ELF files:
174
175 - ``build/<platform>/<build-type>/bl1.bin``
176 - ``build/<platform>/<build-type>/bl2.bin``
177 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
178 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
179
180 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
181 is either ``debug`` or ``release``. The actual number of images might differ
182 depending on the platform.
183
184- Build products for a specific build variant can be removed using:
185
186 ::
187
188 make DEBUG=<D> PLAT=<platform> clean
189
190 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
191
192 The build tree can be removed completely using:
193
194 ::
195
196 make realclean
197
198Summary of build options
199~~~~~~~~~~~~~~~~~~~~~~~~
200
201ARM Trusted Firmware build system supports the following build options. Unless
202mentioned otherwise, these options are expected to be specified at the build
203command line and are not to be modified in any component makefiles. Note that
204the build system doesn't track dependency for build options. Therefore, if any
205of the build options are changed from a previous build, a clean build must be
206performed.
207
208Common build options
209^^^^^^^^^^^^^^^^^^^^
210
211- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
212 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
213 directory containing the SP source, relative to the ``bl32/``; the directory
214 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
215
216- ``ARCH`` : Choose the target build architecture for ARM Trusted Firmware.
217 It can take either ``aarch64`` or ``aarch32`` as values. By default, it is
218 defined to ``aarch64``.
219
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100220- ``ARM_ARCH_MAJOR``: The major version of ARM Architecture to target when
221 compiling ARM Trusted Firmware. Its value must be numeric, and defaults to
Etienne Carriere1374fcb2017-11-08 13:48:40 +0100222 8 . See also, *ARMv8 Architecture Extensions* and
223 *ARMv7 Architecture Extensions* in `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100224
225- ``ARM_ARCH_MINOR``: The minor version of ARM Architecture to target when
226 compiling ARM Trusted Firmware. Its value must be a numeric, and defaults
227 to 0. See also, *ARMv8 Architecture Extensions* in `Firmware Design`_.
228
229- ``ARM_GIC_ARCH``: Choice of ARM GIC architecture version used by the ARM
230 Legacy GIC driver for implementing the platform GIC API. This API is used
231 by the interrupt management framework. Default is 2 (that is, version 2.0).
232 This build option is deprecated.
233
234- ``ARM_PLAT_MT``: This flag determines whether the ARM platform layer has to
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000235 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
236 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
237 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
238 this flag is 0. Note that this option is not used on FVP platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100239
240- ``BL2``: This is an optional build option which specifies the path to BL2
241 image for the ``fip`` target. In this case, the BL2 in the ARM Trusted
242 Firmware will not be built.
243
244- ``BL2U``: This is an optional build option which specifies the path to
245 BL2U image. In this case, the BL2U in the ARM Trusted Firmware will not
246 be built.
247
Roberto Vargasb1584272017-11-20 13:36:10 +0000248- ``BL2_AT_EL3``: This is an optional build option that enables the use of
249 BL2 at EL3 execution level.
250
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100251- ``BL31``: This is an optional build option which specifies the path to
252 BL31 image for the ``fip`` target. In this case, the BL31 in the ARM
253 Trusted Firmware will not be built.
254
255- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
256 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
257 this file name will be used to save the key.
258
259- ``BL32``: This is an optional build option which specifies the path to
260 BL32 image for the ``fip`` target. In this case, the BL32 in the ARM
261 Trusted Firmware will not be built.
262
Summer Qin80726782017-04-20 16:28:39 +0100263- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
264 Trusted OS Extra1 image for the ``fip`` target.
265
266- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
267 Trusted OS Extra2 image for the ``fip`` target.
268
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100269- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
270 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
271 this file name will be used to save the key.
272
273- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
274 ``fip`` target in case the BL2 from ARM Trusted Firmware is used.
275
276- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
277 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
278 this file name will be used to save the key.
279
280- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
281 compilation of each build. It must be set to a C string (including quotes
282 where applicable). Defaults to a string that contains the time and date of
283 the compilation.
284
285- ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF build
286 to be uniquely identified. Defaults to the current git commit id.
287
288- ``CFLAGS``: Extra user options appended on the compiler's command line in
289 addition to the options set by the build system.
290
291- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
292 release several CPUs out of reset. It can take either 0 (several CPUs may be
293 brought up) or 1 (only one CPU will ever be brought up during cold reset).
294 Default is 0. If the platform always brings up a single CPU, there is no
295 need to distinguish between primary and secondary CPUs and the boot path can
296 be optimised. The ``plat_is_my_cpu_primary()`` and
297 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
298 to be implemented in this case.
299
300- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
301 register state when an unexpected exception occurs during execution of
302 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
303 this is only enabled for a debug build of the firmware.
304
305- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
306 certificate generation tool to create new keys in case no valid keys are
307 present or specified. Allowed options are '0' or '1'. Default is '1'.
308
309- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
310 the AArch32 system registers to be included when saving and restoring the
311 CPU context. The option must be set to 0 for AArch64-only platforms (that
312 is on hardware that does not implement AArch32, or at least not at EL1 and
313 higher ELs). Default value is 1.
314
315- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
316 registers to be included when saving and restoring the CPU context. Default
317 is 0.
318
319- ``DEBUG``: Chooses between a debug and release build. It can take either 0
320 (release) or 1 (debug) as values. 0 is the default.
321
322- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
323 the normal boot flow. It must specify the entry point address of the EL3
324 payload. Please refer to the "Booting an EL3 payload" section for more
325 details.
326
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100327- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100328 This is an optional architectural feature available on v8.4 onwards. Some
329 v8.2 implementations also implement an AMU and this option can be used to
330 enable this feature on those systems as well. Default is 0.
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100331
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100332- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
333 are compiled out. For debug builds, this option defaults to 1, and calls to
334 ``assert()`` are left in place. For release builds, this option defaults to 0
335 and calls to ``assert()`` function are compiled out. This option can be set
336 independently of ``DEBUG``. It can also be used to hide any auxiliary code
337 that is only required for the assertion and does not fit in the assertion
338 itself.
339
340- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
341 Measurement Framework(PMF). Default is 0.
342
343- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
344 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
345 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
346 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
347 software.
348
349- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
350 instrumentation which injects timestamp collection points into
351 Trusted Firmware to allow runtime performance to be measured.
352 Currently, only PSCI is instrumented. Enabling this option enables
353 the ``ENABLE_PMF`` build option as well. Default is 0.
354
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100355- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100356 extensions. This is an optional architectural feature for AArch64.
357 The default is 1 but is automatically disabled when the target architecture
358 is AArch32.
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100359
David Cunadoce88eee2017-10-20 11:30:57 +0100360- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
361 (SVE) for the Non-secure world only. SVE is an optional architectural feature
362 for AArch64. Note that when SVE is enabled for the Non-secure world, access
363 to SIMD and floating-point functionality from the Secure world is disabled.
364 This is to avoid corruption of the Non-secure world data in the Z-registers
365 which are aliased by the SIMD and FP registers. The build option is not
366 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
367 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
368 1. The default is 1 but is automatically disabled when the target
369 architecture is AArch32.
370
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100371- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
372 checks in GCC. Allowed values are "all", "strong" and "0" (default).
373 "strong" is the recommended stack protection level if this feature is
374 desired. 0 disables the stack protection. For all values other than 0, the
375 ``plat_get_stack_protector_canary()`` platform hook needs to be implemented.
376 The value is passed as the last component of the option
377 ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
378
379- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
380 deprecated platform APIs, helper functions or drivers within Trusted
381 Firmware as error. It can take the value 1 (flag the use of deprecated
382 APIs as error) or 0. The default is 0.
383
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100384- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
385 targeted at EL3. When set ``0`` (default), no exceptions are expected or
386 handled at EL3, and a panic will result. This is supported only for AArch64
387 builds.
388
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100389- ``FIP_NAME``: This is an optional build option which specifies the FIP
390 filename for the ``fip`` target. Default is ``fip.bin``.
391
392- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
393 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
394
395- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
396 tool to create certificates as per the Chain of Trust described in
397 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
398 include the certificates in the FIP and FWU\_FIP. Default value is '0'.
399
400 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
401 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
402 the corresponding certificates, and to include those certificates in the
403 FIP and FWU\_FIP.
404
405 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
406 images will not include support for Trusted Board Boot. The FIP will still
407 include the corresponding certificates. This FIP can be used to verify the
408 Chain of Trust on the host machine through other mechanisms.
409
410 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
411 images will include support for Trusted Board Boot, but the FIP and FWU\_FIP
412 will not include the corresponding certificates, causing a boot failure.
413
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100414- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
415 inherent support for specific EL3 type interrupts. Setting this build option
416 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
417 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
418 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
419 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
420 the Secure Payload interrupts needs to be synchronously handed over to Secure
421 EL1 for handling. The default value of this option is ``0``, which means the
422 Group 0 interrupts are assumed to be handled by Secure EL1.
423
424 .. __: `platform-interrupt-controller-API.rst`
425 .. __: `interrupt-framework-design.rst`
426
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100427- ``HANDLE_EA_EL3_FIRST``: When defined External Aborts and SError Interrupts
428 will be always trapped in EL3 i.e. in BL31 at runtime.
429
430- ``HW_ASSISTED_COHERENCY``: On most ARM systems to-date, platform-specific
431 software operations are required for CPUs to enter and exit coherency.
432 However, there exists newer systems where CPUs' entry to and exit from
433 coherency is managed in hardware. Such systems require software to only
434 initiate the operations, and the rest is managed in hardware, minimizing
435 active software management. In such systems, this boolean option enables ARM
436 Trusted Firmware to carry out build and run-time optimizations during boot
437 and power management operations. This option defaults to 0 and if it is
438 enabled, then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
439
440- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
441 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
442 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
443 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
444 images.
445
Soby Mathew13b16052017-08-31 11:49:32 +0100446- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
447 used for generating the PKCS keys and subsequent signing of the certificate.
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800448 It accepts 3 values viz. ``rsa``, ``rsa_1_5``, ``ecdsa``. The ``rsa_1_5`` is
Soby Mathew2fd70f62017-08-31 11:50:29 +0100449 the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is
450 retained only for compatibility. The default value of this flag is ``rsa``
451 which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
Soby Mathew13b16052017-08-31 11:49:32 +0100452
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800453- ``HASH_ALG``: This build flag enables the user to select the secure hash
454 algorithm. It accepts 3 values viz. ``sha256``, ``sha384``, ``sha512``.
455 The default value of this flag is ``sha256``.
456
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100457- ``LDFLAGS``: Extra user options appended to the linkers' command line in
458 addition to the one set by the build system.
459
460- ``LOAD_IMAGE_V2``: Boolean option to enable support for new version (v2) of
461 image loading, which provides more flexibility and scalability around what
462 images are loaded and executed during boot. Default is 0.
463 Note: ``TRUSTED_BOARD_BOOT`` is currently only supported for AArch64 when
464 ``LOAD_IMAGE_V2`` is enabled.
465
466- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
467 output compiled into the build. This should be one of the following:
468
469 ::
470
471 0 (LOG_LEVEL_NONE)
472 10 (LOG_LEVEL_NOTICE)
473 20 (LOG_LEVEL_ERROR)
474 30 (LOG_LEVEL_WARNING)
475 40 (LOG_LEVEL_INFO)
476 50 (LOG_LEVEL_VERBOSE)
477
478 All log output up to and including the log level is compiled into the build.
479 The default value is 40 in debug builds and 20 in release builds.
480
481- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
482 specifies the file that contains the Non-Trusted World private key in PEM
483 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
484
485- ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is
486 optional. It is only needed if the platform makefile specifies that it
487 is required in order to build the ``fwu_fip`` target.
488
489- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
490 contents upon world switch. It can take either 0 (don't save and restore) or
491 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
492 wants the timer registers to be saved and restored.
493
494- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
495 the underlying hardware is not a full PL011 UART but a minimally compliant
496 generic UART, which is a subset of the PL011. The driver will not access
497 any register that is not part of the SBSA generic UART specification.
498 Default value is 0 (a full PL011 compliant UART is present).
499
500- ``PLAT``: Choose a platform to build ARM Trusted Firmware for. The chosen
501 platform name must be subdirectory of any depth under ``plat/``, and must
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +0100502 contain a platform makefile named ``platform.mk``. For example to build ARM
503 Trusted Firmware for ARM Juno board select PLAT=juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100504
505- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
506 instead of the normal boot flow. When defined, it must specify the entry
507 point address for the preloaded BL33 image. This option is incompatible with
508 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
509 over ``PRELOADED_BL33_BASE``.
510
511- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
512 vector address can be programmed or is fixed on the platform. It can take
513 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
514 programmable reset address, it is expected that a CPU will start executing
515 code directly at the right address, both on a cold and warm reset. In this
516 case, there is no need to identify the entrypoint on boot and the boot path
517 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
518 does not need to be implemented in this case.
519
520- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
521 possible for the PSCI power-state parameter viz original and extended
522 State-ID formats. This flag if set to 1, configures the generic PSCI layer
523 to use the extended format. The default value of this flag is 0, which
524 means by default the original power-state format is used by the PSCI
525 implementation. This flag should be specified by the platform makefile
526 and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND
527 smc function id. When this option is enabled on ARM platforms, the
528 option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well.
529
530- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
531 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
532 entrypoint) or 1 (CPU reset to BL31 entrypoint).
533 The default value is 0.
534
535- ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided in
536 ARM Trusted Firmware. This flag configures SP\_MIN entrypoint as the CPU
537 reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU
538 reset to BL1 entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default
539 value is 0.
540
541- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
542 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
543 file name will be used to save the key.
544
545- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
546 certificate generation tool to save the keys used to establish the Chain of
547 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
548
549- ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional.
550 If a SCP\_BL2 image is present then this option must be passed for the ``fip``
551 target.
552
553- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
554 file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
555 this file name will be used to save the key.
556
557- ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is
558 optional. It is only needed if the platform makefile specifies that it
559 is required in order to build the ``fwu_fip`` target.
560
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100561- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
562 Delegated Exception Interface to BL31 image. This defaults to ``0``.
563
564 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
565 set to ``1``.
566
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100567- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
568 isolated on separate memory pages. This is a trade-off between security and
569 memory usage. See "Isolating code and read-only data on separate memory
570 pages" section in `Firmware Design`_. This flag is disabled by default and
571 affects all BL images.
572
573- ``SPD``: Choose a Secure Payload Dispatcher component to be built into the
574 Trusted Firmware. This build option is only valid if ``ARCH=aarch64``. The
575 value should be the path to the directory containing the SPD source,
576 relative to ``services/spd/``; the directory is expected to
577 contain a makefile called ``<spd-value>.mk``.
578
579- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
580 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
581 execution in BL1 just before handing over to BL31. At this point, all
582 firmware images have been loaded in memory, and the MMU and caches are
583 turned off. Refer to the "Debugging options" section for more details.
584
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200585- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
586 secure interrupts (caught through the FIQ line). Platforms can enable
587 this directive if they need to handle such interruption. When enabled,
588 the FIQ are handled in monitor mode and non secure world is not allowed
589 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
590 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
591
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100592- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
593 Boot feature. When set to '1', BL1 and BL2 images include support to load
594 and verify the certificates and images in a FIP, and BL1 includes support
595 for the Firmware Update. The default value is '0'. Generation and inclusion
596 of certificates in the FIP and FWU\_FIP depends upon the value of the
597 ``GENERATE_COT`` option.
598
599 Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
600 already exist in disk, they will be overwritten without further notice.
601
602- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
603 specifies the file that contains the Trusted World private key in PEM
604 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
605
606- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
607 synchronous, (see "Initializing a BL32 Image" section in
608 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
609 synchronous method) or 1 (BL32 is initialized using asynchronous method).
610 Default is 0.
611
612- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
613 routing model which routes non-secure interrupts asynchronously from TSP
614 to EL3 causing immediate preemption of TSP. The EL3 is responsible
615 for saving and restoring the TSP context in this routing model. The
616 default routing model (when the value is 0) is to route non-secure
617 interrupts to TSP allowing it to save its context and hand over
618 synchronously to EL3 via an SMC.
619
620- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
621 memory region in the BL memory map or not (see "Use of Coherent memory in
622 Trusted Firmware" section in `Firmware Design`_). It can take the value 1
623 (Coherent memory region is included) or 0 (Coherent memory region is
624 excluded). Default is 1.
625
626- ``V``: Verbose build. If assigned anything other than 0, the build commands
627 are printed. Default is 0.
628
629- ``VERSION_STRING``: String used in the log output for each TF image. Defaults
630 to a string formed by concatenating the version number, build type and build
631 string.
632
633- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
634 the CPU after warm boot. This is applicable for platforms which do not
635 require interconnect programming to enable cache coherency (eg: single
636 cluster platforms). If this option is enabled, then warm boot path
637 enables D-caches immediately after enabling MMU. This option defaults to 0.
638
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100639ARM development platform specific build options
640^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
641
642- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
643 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
644 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
645 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
646 flag.
647
648- ``ARM_BOARD_OPTIMISE_MEM``: Boolean option to enable or disable optimisation
649 of the memory reserved for each image. This affects the maximum size of each
650 BL image as well as the number of allocated memory regions and translation
651 tables. By default this flag is 0, which means it uses the default
652 unoptimised values for these macros. ARM development platforms that wish to
653 optimise memory usage need to set this flag to 1 and must override the
654 related macros.
655
656- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
657 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
658 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
659 match the frame used by the Non-Secure image (normally the Linux kernel).
660 Default is true (access to the frame is allowed).
661
662- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
663 By default, ARM platforms use a watchdog to trigger a system reset in case
664 an error is encountered during the boot process (for example, when an image
665 could not be loaded or authenticated). The watchdog is enabled in the early
666 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
667 Trusted Watchdog may be disabled at build time for testing or development
668 purposes.
669
670- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
671 for the construction of composite state-ID in the power-state parameter.
672 The existing PSCI clients currently do not support this encoding of
673 State-ID yet. Hence this flag is used to configure whether to use the
674 recommended State-ID encoding or not. The default value of this flag is 0,
675 in which case the platform is configured to expect NULL in the State-ID
676 field of power-state parameter.
677
678- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
679 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
680 for ARM platforms. Depending on the selected option, the proper private key
681 must be specified using the ``ROT_KEY`` option when building the Trusted
682 Firmware. This private key will be used by the certificate generation tool
683 to sign the BL2 and Trusted Key certificates. Available options for
684 ``ARM_ROTPK_LOCATION`` are:
685
686 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
687 registers. The private key corresponding to this ROTPK hash is not
688 currently available.
689 - ``devel_rsa`` : return a development public key hash embedded in the BL1
690 and BL2 binaries. This hash has been obtained from the RSA public key
691 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
692 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
693 creating the certificates.
Qixiang Xu1c2aef12017-08-24 15:12:20 +0800694 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
695 and BL2 binaries. This hash has been obtained from the ECDSA public key
696 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
697 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
698 when creating the certificates.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100699
700- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
701
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800702 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100703 - ``tdram`` : Trusted DRAM (if available)
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800704 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
705 configured by the TrustZone controller)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100706
707- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile the Trusted Firmware
708 with version 1 of the translation tables library instead of version 2. It is
709 set to 0 by default, which selects version 2.
710
711- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable Trusted Firmware to invoke
712 ARM® TrustZone® CryptoCell functionality for Trusted Board Boot on capable
713 ARM platforms. If this option is specified, then the path to the CryptoCell
714 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
715
716For a better understanding of these options, the ARM development platform memory
717map is explained in the `Firmware Design`_.
718
719ARM CSS platform specific build options
720^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
721
722- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
723 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
724 compatible change to the MTL protocol, used for AP/SCP communication.
725 Trusted Firmware no longer supports earlier SCP versions. If this option is
726 set to 1 then Trusted Firmware will detect if an earlier version is in use.
727 Default is 1.
728
729- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and
730 SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
731 during boot. Default is 1.
732
Soby Mathew1ced6b82017-06-12 12:37:10 +0100733- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
734 instead of SCPI/BOM driver for communicating with the SCP during power
735 management operations and for SCP RAM Firmware transfer. If this option
736 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100737
738ARM FVP platform specific build options
739^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
740
741- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
742 build the topology tree within Trusted Firmware. By default the
743 Trusted Firmware is configured for dual cluster topology and this option
744 can be used to override the default value.
745
746- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
747 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
748 explained in the options below:
749
750 - ``FVP_CCI`` : The CCI driver is selected. This is the default
751 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
752 - ``FVP_CCN`` : The CCN driver is selected. This is the default
753 if ``FVP_CLUSTER_COUNT`` > 2.
754
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000755- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
756 in the system. This option defaults to 1. Note that the build option
757 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
758
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100759- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
760
761 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
762 - ``FVP_GICV2`` : The GICv2 only driver is selected
763 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
764 - ``FVP_GICV3_LEGACY``: The Legacy GICv3 driver is selected (deprecated)
765 Note: If Trusted Firmware is compiled with this option on FVPs with
766 GICv3 hardware, then it configures the hardware to run in GICv2
767 emulation mode
768
769- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
770 for functions that wait for an arbitrary time length (udelay and mdelay).
771 The default value is 0.
772
773Debugging options
774~~~~~~~~~~~~~~~~~
775
776To compile a debug version and make the build more verbose use
777
778::
779
780 make PLAT=<platform> DEBUG=1 V=1 all
781
782AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
783example DS-5) might not support this and may need an older version of DWARF
784symbols to be emitted by GCC. This can be achieved by using the
785``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
786version to 2 is recommended for DS-5 versions older than 5.16.
787
788When debugging logic problems it might also be useful to disable all compiler
789optimizations by using ``-O0``.
790
791NOTE: Using ``-O0`` could cause output images to be larger and base addresses
792might need to be recalculated (see the **Memory layout on ARM development
793platforms** section in the `Firmware Design`_).
794
795Extra debug options can be passed to the build system by setting ``CFLAGS`` or
796``LDFLAGS``:
797
798.. code:: makefile
799
800 CFLAGS='-O0 -gdwarf-2' \
801 make PLAT=<platform> DEBUG=1 V=1 all
802
803Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
804ignored as the linker is called directly.
805
806It is also possible to introduce an infinite loop to help in debugging the
807post-BL2 phase of the Trusted Firmware. This can be done by rebuilding BL1 with
Douglas Raillard30d7b362017-06-28 16:14:55 +0100808the ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100809section. In this case, the developer may take control of the target using a
810debugger when indicated by the console output. When using DS-5, the following
811commands can be used:
812
813::
814
815 # Stop target execution
816 interrupt
817
818 #
819 # Prepare your debugging environment, e.g. set breakpoints
820 #
821
822 # Jump over the debug loop
823 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
824
825 # Resume execution
826 continue
827
828Building the Test Secure Payload
829~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
830
831The TSP is coupled with a companion runtime service in the BL31 firmware,
832called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
833must be recompiled as well. For more information on SPs and SPDs, see the
834`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
835
836First clean the Trusted Firmware build directory to get rid of any previous
837BL31 binary. Then to build the TSP image use:
838
839::
840
841 make PLAT=<platform> SPD=tspd all
842
843An additional boot loader binary file is created in the ``build`` directory:
844
845::
846
847 build/<platform>/<build-type>/bl32.bin
848
849Checking source code style
850~~~~~~~~~~~~~~~~~~~~~~~~~~
851
852When making changes to the source for submission to the project, the source
853must be in compliance with the Linux style guide, and to assist with this check
854the project Makefile contains two targets, which both utilise the
855``checkpatch.pl`` script that ships with the Linux source tree.
856
857To check the entire source tree, you must first download a copy of
858``checkpatch.pl`` (or the full Linux source), set the ``CHECKPATCH`` environment
859variable to point to the script and build the target checkcodebase:
860
861::
862
863 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
864
865To just check the style on the files that differ between your local branch and
866the remote master, use:
867
868::
869
870 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
871
872If you wish to check your patch against something other than the remote master,
873set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
874is set to ``origin/master``.
875
876Building and using the FIP tool
877~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
878
879Firmware Image Package (FIP) is a packaging format used by the Trusted Firmware
880project to package firmware images in a single binary. The number and type of
881images that should be packed in a FIP is platform specific and may include TF
882images and other firmware images required by the platform. For example, most
883platforms require a BL33 image which corresponds to the normal world bootloader
884(e.g. UEFI or U-Boot).
885
886The TF build system provides the make target ``fip`` to create a FIP file for the
887specified platform using the FIP creation tool included in the TF project.
888Examples below show how to build a FIP file for FVP, packaging TF images and a
889BL33 image.
890
891For AArch64:
892
893::
894
895 make PLAT=fvp BL33=<path/to/bl33.bin> fip
896
897For AArch32:
898
899::
900
901 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip
902
903Note that AArch32 support for Normal world boot loader (BL33), like U-boot or
904UEFI, on FVP is not available upstream. Hence custom solutions are required to
905allow Linux boot on FVP. These instructions assume such a custom boot loader
906(BL33) is available.
907
908The resulting FIP may be found in:
909
910::
911
912 build/fvp/<build-type>/fip.bin
913
914For advanced operations on FIP files, it is also possible to independently build
915the tool and create or modify FIPs using this tool. To do this, follow these
916steps:
917
918It is recommended to remove old artifacts before building the tool:
919
920::
921
922 make -C tools/fiptool clean
923
924Build the tool:
925
926::
927
928 make [DEBUG=1] [V=1] fiptool
929
930The tool binary can be located in:
931
932::
933
934 ./tools/fiptool/fiptool
935
936Invoking the tool with ``--help`` will print a help message with all available
937options.
938
939Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
940
941::
942
943 ./tools/fiptool/fiptool create \
944 --tb-fw build/<platform>/<build-type>/bl2.bin \
945 --soc-fw build/<platform>/<build-type>/bl31.bin \
946 fip.bin
947
948Example 2: view the contents of an existing Firmware package:
949
950::
951
952 ./tools/fiptool/fiptool info <path-to>/fip.bin
953
954Example 3: update the entries of an existing Firmware package:
955
956::
957
958 # Change the BL2 from Debug to Release version
959 ./tools/fiptool/fiptool update \
960 --tb-fw build/<platform>/release/bl2.bin \
961 build/<platform>/debug/fip.bin
962
963Example 4: unpack all entries from an existing Firmware package:
964
965::
966
967 # Images will be unpacked to the working directory
968 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
969
970Example 5: remove an entry from an existing Firmware package:
971
972::
973
974 ./tools/fiptool/fiptool remove \
975 --tb-fw build/<platform>/debug/fip.bin
976
977Note that if the destination FIP file exists, the create, update and
978remove operations will automatically overwrite it.
979
980The unpack operation will fail if the images already exist at the
981destination. In that case, use -f or --force to continue.
982
983More information about FIP can be found in the `Firmware Design`_ document.
984
985Migrating from fip\_create to fiptool
986^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
987
988The previous version of fiptool was called fip\_create. A compatibility script
989that emulates the basic functionality of the previous fip\_create is provided.
990However, users are strongly encouraged to migrate to fiptool.
991
992- To create a new FIP file, replace "fip\_create" with "fiptool create".
993- To update a FIP file, replace "fip\_create" with "fiptool update".
994- To dump the contents of a FIP file, replace "fip\_create --dump"
995 with "fiptool info".
996
997Building FIP images with support for Trusted Board Boot
998~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
999
1000Trusted Board Boot primarily consists of the following two features:
1001
1002- Image Authentication, described in `Trusted Board Boot`_, and
1003- Firmware Update, described in `Firmware Update`_
1004
1005The following steps should be followed to build FIP and (optionally) FWU\_FIP
1006images with support for these features:
1007
1008#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1009 modules by checking out a recent version of the `mbed TLS Repository`_. It
1010 is important to use a version that is compatible with TF and fixes any
1011 known security vulnerabilities. See `mbed TLS Security Center`_ for more
David Cunado82509be2017-12-19 16:33:25 +00001012 information. The latest version of TF is tested with tag ``mbedtls-2.6.0``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001013
1014 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1015 source files the modules depend upon.
1016 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1017 options required to build the mbed TLS sources.
1018
1019 Note that the mbed TLS library is licensed under the Apache version 2.0
1020 license. Using mbed TLS source code will affect the licensing of
1021 Trusted Firmware binaries that are built using this library.
1022
1023#. To build the FIP image, ensure the following command line variables are set
1024 while invoking ``make`` to build Trusted Firmware:
1025
1026 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1027 - ``TRUSTED_BOARD_BOOT=1``
1028 - ``GENERATE_COT=1``
1029
1030 In the case of ARM platforms, the location of the ROTPK hash must also be
1031 specified at build time. Two locations are currently supported (see
1032 ``ARM_ROTPK_LOCATION`` build option):
1033
1034 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1035 root-key storage registers present in the platform. On Juno, this
1036 registers are read-only. On FVP Base and Cortex models, the registers
1037 are read-only, but the value can be specified using the command line
1038 option ``bp.trusted_key_storage.public_key`` when launching the model.
1039 On both Juno and FVP models, the default value corresponds to an
1040 ECDSA-SECP256R1 public key hash, whose private part is not currently
1041 available.
1042
1043 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
1044 in the ARM platform port. The private/public RSA key pair may be
1045 found in ``plat/arm/board/common/rotpk``.
1046
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001047 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
1048 in the ARM platform port. The private/public ECDSA key pair may be
1049 found in ``plat/arm/board/common/rotpk``.
1050
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001051 Example of command line using RSA development keys:
1052
1053 ::
1054
1055 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1056 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1057 ARM_ROTPK_LOCATION=devel_rsa \
1058 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1059 BL33=<path-to>/<bl33_image> \
1060 all fip
1061
1062 The result of this build will be the bl1.bin and the fip.bin binaries. This
1063 FIP will include the certificates corresponding to the Chain of Trust
1064 described in the TBBR-client document. These certificates can also be found
1065 in the output build directory.
1066
1067#. The optional FWU\_FIP contains any additional images to be loaded from
1068 Non-Volatile storage during the `Firmware Update`_ process. To build the
1069 FWU\_FIP, any FWU images required by the platform must be specified on the
1070 command line. On ARM development platforms like Juno, these are:
1071
1072 - NS\_BL2U. The AP non-secure Firmware Updater image.
1073 - SCP\_BL2U. The SCP Firmware Update Configuration image.
1074
1075 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1076 targets using RSA development:
1077
1078 ::
1079
1080 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1081 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1082 ARM_ROTPK_LOCATION=devel_rsa \
1083 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1084 BL33=<path-to>/<bl33_image> \
1085 SCP_BL2=<path-to>/<scp_bl2_image> \
1086 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1087 NS_BL2U=<path-to>/<ns_bl2u_image> \
1088 all fip fwu_fip
1089
1090 Note: The BL2U image will be built by default and added to the FWU\_FIP.
1091 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1092 to the command line above.
1093
1094 Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U,
1095 NS\_BL2U and SCP\_BL2U) is outside the scope of this document.
1096
1097 The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries.
1098 Both the FIP and FWU\_FIP will include the certificates corresponding to the
1099 Chain of Trust described in the TBBR-client document. These certificates
1100 can also be found in the output build directory.
1101
1102Building the Certificate Generation Tool
1103~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1104
1105The ``cert_create`` tool is built as part of the TF build process when the ``fip``
1106make target is specified and TBB is enabled (as described in the previous
1107section), but it can also be built separately with the following command:
1108
1109::
1110
1111 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1112
1113For platforms that do not require their own IDs in certificate files,
1114the generic 'cert\_create' tool can be built with the following command:
1115
1116::
1117
1118 make USE_TBBR_DEFS=1 [DEBUG=1] [V=1] certtool
1119
1120``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1121verbose. The following command should be used to obtain help about the tool:
1122
1123::
1124
1125 ./tools/cert_create/cert_create -h
1126
1127Building a FIP for Juno and FVP
1128-------------------------------
1129
1130This section provides Juno and FVP specific instructions to build Trusted
1131Firmware, obtain the additional required firmware, and pack it all together in
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001132a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001133
David Cunadob2de0992017-06-29 12:01:33 +01001134Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12
1135onwards. Before that release, pre-built binaries are only available for AArch64.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001136
1137Note: follow the full instructions for one platform before switching to a
1138different one. Mixing instructions for different platforms may result in
1139corrupted binaries.
1140
1141#. Clean the working directory
1142
1143 ::
1144
1145 make realclean
1146
1147#. Obtain SCP\_BL2 (Juno) and BL33 (all platforms)
1148
1149 Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP
1150 package included in the Linaro release:
1151
1152 ::
1153
1154 # Build the fiptool
1155 make [DEBUG=1] [V=1] fiptool
1156
1157 # Unpack firmware images from Linaro FIP
1158 ./tools/fiptool/fiptool unpack \
1159 <path/to/linaro/release>/fip.bin
1160
1161 The unpack operation will result in a set of binary images extracted to the
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001162 current working directory. The SCP\_BL2 image corresponds to
1163 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001164
1165 Note: the fiptool will complain if the images to be unpacked already
1166 exist in the current directory. If that is the case, either delete those
1167 files or use the ``--force`` option to overwrite.
1168
1169 Note for AArch32, the instructions below assume that nt-fw.bin is a custom
1170 Normal world boot loader that supports AArch32.
1171
1172#. Build TF images and create a new FIP for FVP
1173
1174 ::
1175
1176 # AArch64
1177 make PLAT=fvp BL33=nt-fw.bin all fip
1178
1179 # AArch32
1180 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1181
1182#. Build TF images and create a new FIP for Juno
1183
1184 For AArch64:
1185
1186 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1187 as a build parameter.
1188
1189 ::
1190
1191 make PLAT=juno all fip \
1192 BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \
1193 SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin
1194
1195 For AArch32:
1196
1197 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1198 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1199 separately for AArch32.
1200
1201 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1202 to the AArch32 Linaro cross compiler.
1203
1204 ::
1205
1206 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1207
1208 - Build BL32 in AArch32.
1209
1210 ::
1211
1212 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1213 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1214
1215 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1216 must point to the AArch64 Linaro cross compiler.
1217
1218 ::
1219
1220 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1221
1222 - The following parameters should be used to build BL1 and BL2 in AArch64
1223 and point to the BL32 file.
1224
1225 ::
1226
1227 make ARCH=aarch64 PLAT=juno LOAD_IMAGE_V2=1 JUNO_AARCH32_EL3_RUNTIME=1 \
1228 BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \
Soby Mathewbf169232017-11-14 14:10:10 +00001229 SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001230 BL32=<path-to-bl32>/bl32.bin all fip
1231
1232The resulting BL1 and FIP images may be found in:
1233
1234::
1235
1236 # Juno
1237 ./build/juno/release/bl1.bin
1238 ./build/juno/release/fip.bin
1239
1240 # FVP
1241 ./build/fvp/release/bl1.bin
1242 ./build/fvp/release/fip.bin
1243
Roberto Vargas096f3a02017-10-17 10:19:00 +01001244
1245Booting Firmware Update images
1246-------------------------------------
1247
1248When Firmware Update (FWU) is enabled there are at least 2 new images
1249that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1250FWU FIP.
1251
1252Juno
1253~~~~
1254
1255The new images must be programmed in flash memory by adding
1256an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1257on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1258Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1259programming" for more information. User should ensure these do not
1260overlap with any other entries in the file.
1261
1262::
1263
1264 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1265 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1266 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1267 NOR10LOAD: 00000000 ;Image Load Address
1268 NOR10ENTRY: 00000000 ;Image Entry Point
1269
1270 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1271 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1272 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1273 NOR11LOAD: 00000000 ;Image Load Address
1274
1275The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1276In the same way, the address ns_bl2u_base_address is the value of
1277NS_BL2U_BASE - 0x8000000.
1278
1279FVP
1280~~~
1281
1282The additional fip images must be loaded with:
1283
1284::
1285
1286 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1287 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1288
1289The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1290In the same way, the address ns_bl2u_base_address is the value of
1291NS_BL2U_BASE.
1292
1293
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001294EL3 payloads alternative boot flow
1295----------------------------------
1296
1297On a pre-production system, the ability to execute arbitrary, bare-metal code at
1298the highest exception level is required. It allows full, direct access to the
1299hardware, for example to run silicon soak tests.
1300
1301Although it is possible to implement some baremetal secure firmware from
1302scratch, this is a complex task on some platforms, depending on the level of
1303configuration required to put the system in the expected state.
1304
1305Rather than booting a baremetal application, a possible compromise is to boot
1306``EL3 payloads`` through the Trusted Firmware instead. This is implemented as an
1307alternative boot flow, where a modified BL2 boots an EL3 payload, instead of
1308loading the other BL images and passing control to BL31. It reduces the
1309complexity of developing EL3 baremetal code by:
1310
1311- putting the system into a known architectural state;
1312- taking care of platform secure world initialization;
1313- loading the SCP\_BL2 image if required by the platform.
1314
1315When booting an EL3 payload on ARM standard platforms, the configuration of the
1316TrustZone controller is simplified such that only region 0 is enabled and is
1317configured to permit secure access only. This gives full access to the whole
1318DRAM to the EL3 payload.
1319
1320The system is left in the same state as when entering BL31 in the default boot
1321flow. In particular:
1322
1323- Running in EL3;
1324- Current state is AArch64;
1325- Little-endian data access;
1326- All exceptions disabled;
1327- MMU disabled;
1328- Caches disabled.
1329
1330Booting an EL3 payload
1331~~~~~~~~~~~~~~~~~~~~~~
1332
1333The EL3 payload image is a standalone image and is not part of the FIP. It is
1334not loaded by the Trusted Firmware. Therefore, there are 2 possible scenarios:
1335
1336- The EL3 payload may reside in non-volatile memory (NVM) and execute in
1337 place. In this case, booting it is just a matter of specifying the right
1338 address in NVM through ``EL3_PAYLOAD_BASE`` when building the TF.
1339
1340- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1341 run-time.
1342
1343To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1344used. The infinite loop that it introduces in BL1 stops execution at the right
1345moment for a debugger to take control of the target and load the payload (for
1346example, over JTAG).
1347
1348It is expected that this loading method will work in most cases, as a debugger
1349connection is usually available in a pre-production system. The user is free to
1350use any other platform-specific mechanism to load the EL3 payload, though.
1351
1352Booting an EL3 payload on FVP
1353^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1354
1355The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1356the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1357is undefined on the FVP platform and the FVP platform code doesn't clear it.
1358Therefore, one must modify the way the model is normally invoked in order to
1359clear the mailbox at start-up.
1360
1361One way to do that is to create an 8-byte file containing all zero bytes using
1362the following command:
1363
1364::
1365
1366 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1367
1368and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1369using the following model parameters:
1370
1371::
1372
1373 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1374 --data=mailbox.dat@0x04000000 [Foundation FVP]
1375
1376To provide the model with the EL3 payload image, the following methods may be
1377used:
1378
1379#. If the EL3 payload is able to execute in place, it may be programmed into
1380 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1381 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1382 used for the FIP):
1383
1384 ::
1385
1386 -C bp.flashloader1.fname="/path/to/el3-payload"
1387
1388 On Foundation FVP, there is no flash loader component and the EL3 payload
1389 may be programmed anywhere in flash using method 3 below.
1390
1391#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1392 command may be used to load the EL3 payload ELF image over JTAG:
1393
1394 ::
1395
1396 load /path/to/el3-payload.elf
1397
1398#. The EL3 payload may be pre-loaded in volatile memory using the following
1399 model parameters:
1400
1401 ::
1402
1403 --data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs]
1404 --data="/path/to/el3-payload"@address [Foundation FVP]
1405
1406 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
1407 used when building the Trusted Firmware.
1408
1409Booting an EL3 payload on Juno
1410^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1411
1412If the EL3 payload is able to execute in place, it may be programmed in flash
1413memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1414on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1415Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1416programming" for more information.
1417
1418Alternatively, the same DS-5 command mentioned in the FVP section above can
1419be used to load the EL3 payload's ELF file over JTAG on Juno.
1420
1421Preloaded BL33 alternative boot flow
1422------------------------------------
1423
1424Some platforms have the ability to preload BL33 into memory instead of relying
1425on Trusted Firmware to load it. This may simplify packaging of the normal world
1426code and improve performance in a development environment. When secure world
1427cold boot is complete, Trusted Firmware simply jumps to a BL33 base address
1428provided at build time.
1429
1430For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
1431used when compiling the Trusted Firmware. For example, the following command
1432will create a FIP without a BL33 and prepare to jump to a BL33 image loaded at
1433address 0x80000000:
1434
1435::
1436
1437 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1438
1439Boot of a preloaded bootwrapped kernel image on Base FVP
1440~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1441
1442The following example uses the AArch64 boot wrapper. This simplifies normal
1443world booting while also making use of TF features. It can be obtained from its
1444repository with:
1445
1446::
1447
1448 git clone git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git
1449
1450After compiling it, an ELF file is generated. It can be loaded with the
1451following command:
1452
1453::
1454
1455 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1456 -C bp.secureflashloader.fname=bl1.bin \
1457 -C bp.flashloader0.fname=fip.bin \
1458 -a cluster0.cpu0=<bootwrapped-kernel.elf> \
1459 --start cluster0.cpu0=0x0
1460
1461The ``-a cluster0.cpu0=<bootwrapped-kernel.elf>`` option loads the ELF file. It
1462also sets the PC register to the ELF entry point address, which is not the
1463desired behaviour, so the ``--start cluster0.cpu0=0x0`` option forces the PC back
1464to 0x0 (the BL1 entry point address) on CPU #0. The ``PRELOADED_BL33_BASE`` define
1465used when compiling the FIP must match the ELF entry point.
1466
1467Boot of a preloaded bootwrapped kernel image on Juno
1468~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1469
1470The procedure to obtain and compile the boot wrapper is very similar to the case
1471of the FVP. The execution must be stopped at the end of bl2\_main(), and the
1472loading method explained above in the EL3 payload boot flow section may be used
1473to load the ELF file over JTAG on Juno.
1474
1475Running the software on FVP
1476---------------------------
1477
1478The latest version of the AArch64 build of ARM Trusted Firmware has been tested
1479on the following ARM FVPs (64-bit host machine only).
1480
David Cunado82509be2017-12-19 16:33:25 +00001481NOTE: Unless otherwise stated, the model version is Version 11.2 Build 11.2.33.
David Cunado124415e2017-06-27 17:31:12 +01001482
1483- ``Foundation_Platform``
David Cunado82509be2017-12-19 16:33:25 +00001484- ``FVP_Base_AEMv8A-AEMv8A`` (Version 9.0, Build 0.8.9005)
David Cunado124415e2017-06-27 17:31:12 +01001485- ``FVP_Base_Cortex-A35x4``
1486- ``FVP_Base_Cortex-A53x4``
1487- ``FVP_Base_Cortex-A57x4-A53x4``
1488- ``FVP_Base_Cortex-A57x4``
1489- ``FVP_Base_Cortex-A72x4-A53x4``
1490- ``FVP_Base_Cortex-A72x4``
1491- ``FVP_Base_Cortex-A73x4-A53x4``
1492- ``FVP_Base_Cortex-A73x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001493
1494The latest version of the AArch32 build of ARM Trusted Firmware has been tested
1495on the following ARM FVPs (64-bit host machine only).
1496
David Cunado82509be2017-12-19 16:33:25 +00001497- ``FVP_Base_AEMv8A-AEMv8A`` (Version 9.0, Build 0.8.9005)
David Cunado124415e2017-06-27 17:31:12 +01001498- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001499
1500NOTE: The build numbers quoted above are those reported by launching the FVP
1501with the ``--version`` parameter.
1502
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001503NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full
1504file systems that can be downloaded separately. To run an FVP with a virtio
1505file system image an additional FVP configuration option
1506``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1507used.
1508
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001509NOTE: The software will not work on Version 1.0 of the Foundation FVP.
1510The commands below would report an ``unhandled argument`` error in this case.
1511
1512NOTE: FVPs can be launched with ``--cadi-server`` option such that a
1513CADI-compliant debugger (for example, ARM DS-5) can connect to and control its
1514execution.
1515
Eleanor Bonnicie124dc42017-10-04 15:03:33 +01001516NOTE: Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
David Cunado97309462017-07-31 12:24:51 +01001517the internal synchronisation timings changed compared to older versions of the
1518models. The models can be launched with ``-Q 100`` option if they are required
1519to match the run time characteristics of the older versions.
1520
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001521The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
1522downloaded for free from `ARM's website`_.
1523
David Cunado124415e2017-06-27 17:31:12 +01001524The Cortex-A models listed above are also available to download from
1525`ARM's website`_.
1526
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001527Please refer to the FVP documentation for a detailed description of the model
1528parameter options. A brief description of the important ones that affect the ARM
1529Trusted Firmware and normal world software behavior is provided below.
1530
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001531Obtaining the Flattened Device Trees
1532~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1533
1534Depending on the FVP configuration and Linux configuration used, different
1535FDT files are required. FDTs for the Foundation and Base FVPs can be found in
1536the Trusted Firmware source directory under ``fdts/``. The Foundation FVP has a
1537subset of the Base FVP components. For example, the Foundation FVP lacks CLCD
1538and MMC support, and has only one CPU cluster.
1539
1540Note: It is not recommended to use the FDTs built along the kernel because not
1541all FDTs are available from there.
1542
1543- ``fvp-base-gicv2-psci.dtb``
1544
1545 For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
1546 Base memory map configuration.
1547
1548- ``fvp-base-gicv2-psci-aarch32.dtb``
1549
1550 For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state
1551 with Base memory map configuration.
1552
1553- ``fvp-base-gicv3-psci.dtb``
1554
1555 (Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base
1556 memory map configuration and Linux GICv3 support.
1557
1558- ``fvp-base-gicv3-psci-aarch32.dtb``
1559
1560 For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state
1561 with Base memory map configuration and Linux GICv3 support.
1562
1563- ``fvp-foundation-gicv2-psci.dtb``
1564
1565 For use with Foundation FVP with Base memory map configuration.
1566
1567- ``fvp-foundation-gicv3-psci.dtb``
1568
1569 (Default) For use with Foundation FVP with Base memory map configuration
1570 and Linux GICv3 support.
1571
1572Running on the Foundation FVP with reset to BL1 entrypoint
1573~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1574
1575The following ``Foundation_Platform`` parameters should be used to boot Linux with
15764 CPUs using the AArch64 build of ARM Trusted Firmware.
1577
1578::
1579
1580 <path-to>/Foundation_Platform \
1581 --cores=4 \
1582 --secure-memory \
1583 --visualization \
1584 --gicv3 \
1585 --data="<path-to>/<bl1-binary>"@0x0 \
1586 --data="<path-to>/<FIP-binary>"@0x08000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001587 --data="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001588 --data="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001589 --data="<path-to>/<ramdisk-binary>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001590
1591Notes:
1592
1593- BL1 is loaded at the start of the Trusted ROM.
1594- The Firmware Image Package is loaded at the start of NOR FLASH0.
1595- The Linux kernel image and device tree are loaded in DRAM.
1596- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1597 and enable the GICv3 device in the model. Note that without this option,
1598 the Foundation FVP defaults to legacy (Versatile Express) memory map which
1599 is not supported by ARM Trusted Firmware.
1600
1601Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1602~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1603
1604The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1605with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1606
1607::
1608
1609 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1610 -C pctl.startup=0.0.0.0 \
1611 -C bp.secure_memory=1 \
1612 -C bp.tzc_400.diagnostics=1 \
1613 -C cluster0.NUM_CORES=4 \
1614 -C cluster1.NUM_CORES=4 \
1615 -C cache_state_modelled=1 \
1616 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1617 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001618 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001619 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001620 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001621
1622Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1623~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1624
1625The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1626with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
1627
1628::
1629
1630 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1631 -C pctl.startup=0.0.0.0 \
1632 -C bp.secure_memory=1 \
1633 -C bp.tzc_400.diagnostics=1 \
1634 -C cluster0.NUM_CORES=4 \
1635 -C cluster1.NUM_CORES=4 \
1636 -C cache_state_modelled=1 \
1637 -C cluster0.cpu0.CONFIG64=0 \
1638 -C cluster0.cpu1.CONFIG64=0 \
1639 -C cluster0.cpu2.CONFIG64=0 \
1640 -C cluster0.cpu3.CONFIG64=0 \
1641 -C cluster1.cpu0.CONFIG64=0 \
1642 -C cluster1.cpu1.CONFIG64=0 \
1643 -C cluster1.cpu2.CONFIG64=0 \
1644 -C cluster1.cpu3.CONFIG64=0 \
1645 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1646 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001647 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001648 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001649 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001650
1651Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1652~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1653
1654The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
1655boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1656
1657::
1658
1659 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1660 -C pctl.startup=0.0.0.0 \
1661 -C bp.secure_memory=1 \
1662 -C bp.tzc_400.diagnostics=1 \
1663 -C cache_state_modelled=1 \
1664 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1665 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001666 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001667 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001668 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001669
1670Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1671~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1672
1673The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
1674boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
1675
1676::
1677
1678 <path-to>/FVP_Base_Cortex-A32x4 \
1679 -C pctl.startup=0.0.0.0 \
1680 -C bp.secure_memory=1 \
1681 -C bp.tzc_400.diagnostics=1 \
1682 -C cache_state_modelled=1 \
1683 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1684 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001685 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001686 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001687 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001688
1689Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1690~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1691
1692The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1693with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1694
1695::
1696
1697 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1698 -C pctl.startup=0.0.0.0 \
1699 -C bp.secure_memory=1 \
1700 -C bp.tzc_400.diagnostics=1 \
1701 -C cluster0.NUM_CORES=4 \
1702 -C cluster1.NUM_CORES=4 \
1703 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001704 -C cluster0.cpu0.RVBAR=0x04020000 \
1705 -C cluster0.cpu1.RVBAR=0x04020000 \
1706 -C cluster0.cpu2.RVBAR=0x04020000 \
1707 -C cluster0.cpu3.RVBAR=0x04020000 \
1708 -C cluster1.cpu0.RVBAR=0x04020000 \
1709 -C cluster1.cpu1.RVBAR=0x04020000 \
1710 -C cluster1.cpu2.RVBAR=0x04020000 \
1711 -C cluster1.cpu3.RVBAR=0x04020000 \
1712 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001713 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1714 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001715 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001716 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001717 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001718
1719Notes:
1720
1721- Since a FIP is not loaded when using BL31 as reset entrypoint, the
1722 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
1723 parameter is needed to load the individual bootloader images in memory.
1724 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
1725 Payload.
1726
1727- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
1728 X and Y are the cluster and CPU numbers respectively, is used to set the
1729 reset vector for each core.
1730
1731- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
1732 changing the value of
1733 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
1734 ``BL32_BASE``.
1735
1736Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1737~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1738
1739The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1740with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
1741
1742::
1743
1744 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1745 -C pctl.startup=0.0.0.0 \
1746 -C bp.secure_memory=1 \
1747 -C bp.tzc_400.diagnostics=1 \
1748 -C cluster0.NUM_CORES=4 \
1749 -C cluster1.NUM_CORES=4 \
1750 -C cache_state_modelled=1 \
1751 -C cluster0.cpu0.CONFIG64=0 \
1752 -C cluster0.cpu1.CONFIG64=0 \
1753 -C cluster0.cpu2.CONFIG64=0 \
1754 -C cluster0.cpu3.CONFIG64=0 \
1755 -C cluster1.cpu0.CONFIG64=0 \
1756 -C cluster1.cpu1.CONFIG64=0 \
1757 -C cluster1.cpu2.CONFIG64=0 \
1758 -C cluster1.cpu3.CONFIG64=0 \
1759 -C cluster0.cpu0.RVBAR=0x04001000 \
1760 -C cluster0.cpu1.RVBAR=0x04001000 \
1761 -C cluster0.cpu2.RVBAR=0x04001000 \
1762 -C cluster0.cpu3.RVBAR=0x04001000 \
1763 -C cluster1.cpu0.RVBAR=0x04001000 \
1764 -C cluster1.cpu1.RVBAR=0x04001000 \
1765 -C cluster1.cpu2.RVBAR=0x04001000 \
1766 -C cluster1.cpu3.RVBAR=0x04001000 \
1767 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1768 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001769 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001770 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001771 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001772
1773Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
1774It should match the address programmed into the RVBAR register as well.
1775
1776Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
1777~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1778
1779The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
1780boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1781
1782::
1783
1784 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1785 -C pctl.startup=0.0.0.0 \
1786 -C bp.secure_memory=1 \
1787 -C bp.tzc_400.diagnostics=1 \
1788 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001789 -C cluster0.cpu0.RVBARADDR=0x04020000 \
1790 -C cluster0.cpu1.RVBARADDR=0x04020000 \
1791 -C cluster0.cpu2.RVBARADDR=0x04020000 \
1792 -C cluster0.cpu3.RVBARADDR=0x04020000 \
1793 -C cluster1.cpu0.RVBARADDR=0x04020000 \
1794 -C cluster1.cpu1.RVBARADDR=0x04020000 \
1795 -C cluster1.cpu2.RVBARADDR=0x04020000 \
1796 -C cluster1.cpu3.RVBARADDR=0x04020000 \
1797 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001798 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1799 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001800 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001801 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001802 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001803
1804Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1805~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1806
1807The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
1808boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
1809
1810::
1811
1812 <path-to>/FVP_Base_Cortex-A32x4 \
1813 -C pctl.startup=0.0.0.0 \
1814 -C bp.secure_memory=1 \
1815 -C bp.tzc_400.diagnostics=1 \
1816 -C cache_state_modelled=1 \
1817 -C cluster0.cpu0.RVBARADDR=0x04001000 \
1818 -C cluster0.cpu1.RVBARADDR=0x04001000 \
1819 -C cluster0.cpu2.RVBARADDR=0x04001000 \
1820 -C cluster0.cpu3.RVBARADDR=0x04001000 \
1821 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1822 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001823 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001824 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001825 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001826
1827Running the software on Juno
1828----------------------------
1829
David Cunadob2de0992017-06-29 12:01:33 +01001830This version of the ARM Trusted Firmware has been tested on variants r0, r1 and
1831r2 of Juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001832
1833To execute the software stack on Juno, the version of the Juno board recovery
1834image indicated in the `Linaro Release Notes`_ must be installed. If you have an
1835earlier version installed or are unsure which version is installed, please
1836re-install the recovery image by following the
1837`Instructions for using Linaro's deliverables on Juno`_.
1838
1839Preparing Trusted Firmware images
1840~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1841
1842After building Trusted Firmware, the files ``bl1.bin`` and ``fip.bin`` need copying
1843to the ``SOFTWARE/`` directory of the Juno SD card.
1844
1845Other Juno software information
1846~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1847
1848Please visit the `ARM Platforms Portal`_ to get support and obtain any other Juno
1849software information. Please also refer to the `Juno Getting Started Guide`_ to
1850get more detailed information about the Juno ARM development platform and how to
1851configure it.
1852
1853Testing SYSTEM SUSPEND on Juno
1854~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1855
1856The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
1857to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
1858on Juno, at the linux shell prompt, issue the following command:
1859
1860::
1861
1862 echo +10 > /sys/class/rtc/rtc0/wakealarm
1863 echo -n mem > /sys/power/state
1864
1865The Juno board should suspend to RAM and then wakeup after 10 seconds due to
1866wakeup interrupt from RTC.
1867
1868--------------
1869
1870*Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.*
1871
David Cunadob2de0992017-06-29 12:01:33 +01001872.. _Linaro: `Linaro Release Notes`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001873.. _Linaro Release: `Linaro Release Notes`_
David Cunado82509be2017-12-19 16:33:25 +00001874.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes
1875.. _Linaro Release 17.10: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes#1710
1876.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/linaro-software-deliverables
1877.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001878.. _ARM Platforms Portal: https://community.arm.com/dev-platforms/
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001879.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01001880.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001881.. _here: psci-lib-integration-guide.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001882.. _Trusted Board Boot: trusted-board-boot.rst
1883.. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001884.. _Firmware Update: firmware-update.rst
1885.. _Firmware Design: firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001886.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
1887.. _mbed TLS Security Center: https://tls.mbed.org/security
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001888.. _ARM's website: `FVP models`_
1889.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001890.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
David Cunadob2de0992017-06-29 12:01:33 +01001891.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf