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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
Tanmay Shahfdae9e82022-08-26 15:06:00 -07003 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
Akshay Belsare589ccce2023-05-08 19:00:53 +05304 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05305 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef VERSAL_DEF_H
10#define VERSAL_DEF_H
11
Manish V Badarkhe55861512020-03-27 13:25:51 +000012#include <plat/arm/common/smccc_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <plat/common/common_def.h>
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053014
Akshay Belsare589ccce2023-05-08 19:00:53 +053015#define PLATFORM_MASK GENMASK(27U, 24U)
16#define PLATFORM_VERSION_MASK GENMASK(31U, 28U)
17
Tanmay Shahfdae9e82022-08-26 15:06:00 -070018/* number of interrupt handlers. increase as required */
19#define MAX_INTR_EL3 2
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053020/* List all consoles */
21#define VERSAL_CONSOLE_ID_pl011 1
22#define VERSAL_CONSOLE_ID_pl011_0 1
23#define VERSAL_CONSOLE_ID_pl011_1 2
24#define VERSAL_CONSOLE_ID_dcc 3
25
Michal Simekc56e5482023-09-27 13:58:06 +020026#define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053027
28/* List all supported platforms */
29#define VERSAL_PLATFORM_ID_versal_virt 1
Venkatesh Yadav Abbarapu9c3b77b2022-04-13 09:04:53 +053030#define VERSAL_PLATFORM_ID_spp_itr6 2
31#define VERSAL_PLATFORM_ID_emu_itr6 3
Siva Durga Prasad Paladugu2f4cc712019-05-03 16:35:25 +053032#define VERSAL_PLATFORM_ID_silicon 4
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053033
34#define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM)
35
36/* Firmware Image Package */
37#define VERSAL_PRIMARY_CPU 0
38
39/*******************************************************************************
40 * memory map related constants
41 ******************************************************************************/
42#define DEVICE0_BASE 0xFF000000
43#define DEVICE0_SIZE 0x00E00000
44#define DEVICE1_BASE 0xF9000000
45#define DEVICE1_SIZE 0x00800000
46
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053047/*******************************************************************************
48 * IRQ constants
49 ******************************************************************************/
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -070050#define VERSAL_IRQ_SEC_PHY_TIMER U(29)
Prasad Kummari6dee9fb2023-10-31 15:20:00 +053051#define ARM_IRQ_SEC_PHY_TIMER 29
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053052
53/*******************************************************************************
Tejas Patel54d13192019-02-27 18:44:55 +053054 * CCI-400 related constants
55 ******************************************************************************/
56#define PLAT_ARM_CCI_BASE 0xFD000000
Michal Simek467e16e2023-04-14 08:39:49 +020057#define PLAT_ARM_CCI_SIZE 0x00100000
Tejas Patel54d13192019-02-27 18:44:55 +053058#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
59#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5
60
61/*******************************************************************************
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053062 * UART related constants
63 ******************************************************************************/
64#define VERSAL_UART0_BASE 0xFF000000
65#define VERSAL_UART1_BASE 0xFF010000
66
Michal Simekc56e5482023-09-27 13:58:06 +020067#if CONSOLE_IS(pl011) || CONSOLE_IS(dcc)
68# define UART_BASE VERSAL_UART0_BASE
69#elif CONSOLE_IS(pl011_1)
70# define UART_BASE VERSAL_UART1_BASE
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053071#else
72# error "invalid VERSAL_CONSOLE"
73#endif
74
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053075/*******************************************************************************
76 * Platform related constants
77 ******************************************************************************/
78#if VERSAL_PLATFORM_IS(versal_virt)
79# define PLATFORM_NAME "Versal Virt"
Michal Simekc56e5482023-09-27 13:58:06 +020080# define UART_CLOCK 25000000
81# define UART_BAUDRATE 115200
Siva Durga Prasad Paladugu10161e52019-04-27 11:23:20 +053082# define VERSAL_CPU_CLOCK 2720000
Siva Durga Prasad Paladugu2f4cc712019-05-03 16:35:25 +053083#elif VERSAL_PLATFORM_IS(silicon)
84# define PLATFORM_NAME "Versal Silicon"
Michal Simekc56e5482023-09-27 13:58:06 +020085# define UART_CLOCK 100000000
86# define UART_BAUDRATE 115200
Siva Durga Prasad Paladugu2f4cc712019-05-03 16:35:25 +053087# define VERSAL_CPU_CLOCK 100000000
Venkatesh Yadav Abbarapu9c3b77b2022-04-13 09:04:53 +053088#elif VERSAL_PLATFORM_IS(spp_itr6)
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +053089# define PLATFORM_NAME "SPP ITR6"
Michal Simekc56e5482023-09-27 13:58:06 +020090# define UART_CLOCK 25000000
91# define UART_BAUDRATE 115200
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +053092# define VERSAL_CPU_CLOCK 2720000
Venkatesh Yadav Abbarapu9c3b77b2022-04-13 09:04:53 +053093#elif VERSAL_PLATFORM_IS(emu_itr6)
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +053094# define PLATFORM_NAME "EMU ITR6"
Michal Simekc56e5482023-09-27 13:58:06 +020095# define UART_CLOCK 212000
96# define UART_BAUDRATE 9600
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +053097# define VERSAL_CPU_CLOCK 212000
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053098#endif
99
100/* Access control register defines */
101#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
102#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
103
104/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
105#define CRF_BASE 0xFD1A0000
106#define CRF_SIZE 0x00600000
107
108/* CRF registers and bitfields */
109#define CRF_RST_APU (CRF_BASE + 0X00000300)
110
111#define CRF_RST_APU_ACPU_RESET (1 << 0)
112#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10)
113
114/* APU registers and bitfields */
Abhyuday Godhasaraedc38ae2021-08-04 23:58:46 -0700115#define FPD_APU_BASE 0xFD5C0000U
116#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U)
117#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U)
118#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U)
119#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530120
Abhyuday Godhasaraedc38ae2021-08-04 23:58:46 -0700121#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U
122#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U
123#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530124
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700125/* PMC registers and bitfields */
Abhyuday Godhasaraedc38ae2021-08-04 23:58:46 -0700126#define PMC_GLOBAL_BASE 0xF1110000U
127#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U)
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700128
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530129#endif /* VERSAL_DEF_H */