Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | b226a4d | 2014-05-16 14:08:45 +0100 | [diff] [blame] | 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 33 | #include <assert.h> |
Vikram Kanigiri | 725b133 | 2015-03-04 10:34:27 +0000 | [diff] [blame] | 34 | #include <bl_common.h> |
Lin Ma | 741a382 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 35 | #include <cassert.h> |
Soby Mathew | c9bac9c | 2016-01-19 17:52:28 +0000 | [diff] [blame] | 36 | #include <debug.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 37 | #include <platform_def.h> |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 38 | #include <string.h> |
| 39 | #include <xlat_tables.h> |
| 40 | |
Soby Mathew | c9bac9c | 2016-01-19 17:52:28 +0000 | [diff] [blame] | 41 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
| 42 | #define LVL0_SPACER "" |
| 43 | #define LVL1_SPACER " " |
| 44 | #define LVL2_SPACER " " |
| 45 | #define LVL3_SPACER " " |
| 46 | #define get_level_spacer(level) \ |
| 47 | (((level) == 0) ? LVL0_SPACER : \ |
| 48 | (((level) == 1) ? LVL1_SPACER : \ |
| 49 | (((level) == 2) ? LVL2_SPACER : LVL3_SPACER))) |
| 50 | #define debug_print(...) tf_printf(__VA_ARGS__) |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 51 | #else |
| 52 | #define debug_print(...) ((void)0) |
| 53 | #endif |
| 54 | |
Kristina Martsenko | ed0995c | 2016-02-11 18:11:56 +0000 | [diff] [blame] | 55 | #define IS_POWER_OF_TWO(x) (((x) & ((x) - 1)) == 0) |
| 56 | |
| 57 | /* |
| 58 | * The virtual address space size must be a power of two (as set in TCR.T0SZ). |
| 59 | * As we start the initial lookup at level 1, it must also be between 2 GB and |
| 60 | * 512 GB (with the virtual address size therefore 31 to 39 bits). See section |
| 61 | * D4.2.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.i) for more |
| 62 | * information. |
| 63 | */ |
| 64 | CASSERT(ADDR_SPACE_SIZE >= (1ull << 31) && ADDR_SPACE_SIZE <= (1ull << 39) && |
| 65 | IS_POWER_OF_TWO(ADDR_SPACE_SIZE), assert_valid_addr_space_size); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 66 | |
| 67 | #define UNSET_DESC ~0ul |
| 68 | |
| 69 | #define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) |
| 70 | |
Dan Handley | b226a4d | 2014-05-16 14:08:45 +0100 | [diff] [blame] | 71 | static uint64_t l1_xlation_table[NUM_L1_ENTRIES] |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 72 | __aligned(NUM_L1_ENTRIES * sizeof(uint64_t)); |
| 73 | |
| 74 | static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] |
Soren Brinkmann | 46dd170 | 2016-01-14 10:11:05 -0800 | [diff] [blame] | 75 | __aligned(XLAT_TABLE_SIZE) __section("xlat_table"); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 76 | |
| 77 | static unsigned next_xlat; |
Lin Ma | 741a382 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 78 | static unsigned long max_pa; |
| 79 | static unsigned long max_va; |
| 80 | static unsigned long tcr_ps_bits; |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 81 | |
| 82 | /* |
| 83 | * Array of all memory regions stored in order of ascending base address. |
| 84 | * The list is terminated by the first entry with size == 0. |
| 85 | */ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 86 | static mmap_region_t mmap[MAX_MMAP_REGIONS + 1]; |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 87 | |
| 88 | |
| 89 | static void print_mmap(void) |
| 90 | { |
Soby Mathew | c9bac9c | 2016-01-19 17:52:28 +0000 | [diff] [blame] | 91 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 92 | debug_print("mmap:\n"); |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 93 | mmap_region_t *mm = mmap; |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 94 | while (mm->size) { |
Soby Mathew | c9bac9c | 2016-01-19 17:52:28 +0000 | [diff] [blame] | 95 | debug_print(" VA:0x%lx PA:0x%lx size:0x%lx attr:0x%x\n", |
| 96 | mm->base_va, mm->base_pa, mm->size, mm->attr); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 97 | ++mm; |
| 98 | }; |
| 99 | debug_print("\n"); |
| 100 | #endif |
| 101 | } |
| 102 | |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 103 | void mmap_add_region(unsigned long base_pa, unsigned long base_va, |
| 104 | unsigned long size, unsigned attr) |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 105 | { |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 106 | mmap_region_t *mm = mmap; |
Vikram Kanigiri | 725b133 | 2015-03-04 10:34:27 +0000 | [diff] [blame] | 107 | mmap_region_t *mm_last = mm + ARRAY_SIZE(mmap) - 1; |
Lin Ma | 741a382 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 108 | unsigned long pa_end = base_pa + size - 1; |
| 109 | unsigned long va_end = base_va + size - 1; |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 110 | |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 111 | assert(IS_PAGE_ALIGNED(base_pa)); |
| 112 | assert(IS_PAGE_ALIGNED(base_va)); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 113 | assert(IS_PAGE_ALIGNED(size)); |
| 114 | |
| 115 | if (!size) |
| 116 | return; |
| 117 | |
| 118 | /* Find correct place in mmap to insert new region */ |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 119 | while (mm->base_va < base_va && mm->size) |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 120 | ++mm; |
| 121 | |
| 122 | /* Make room for new region by moving other regions up by one place */ |
| 123 | memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm); |
| 124 | |
| 125 | /* Check we haven't lost the empty sentinal from the end of the array */ |
| 126 | assert(mm_last->size == 0); |
| 127 | |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 128 | mm->base_pa = base_pa; |
| 129 | mm->base_va = base_va; |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 130 | mm->size = size; |
| 131 | mm->attr = attr; |
Lin Ma | 741a382 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 132 | |
| 133 | if (pa_end > max_pa) |
| 134 | max_pa = pa_end; |
| 135 | if (va_end > max_va) |
| 136 | max_va = va_end; |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 137 | } |
| 138 | |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 139 | void mmap_add(const mmap_region_t *mm) |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 140 | { |
| 141 | while (mm->size) { |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 142 | mmap_add_region(mm->base_pa, mm->base_va, mm->size, mm->attr); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 143 | ++mm; |
| 144 | } |
| 145 | } |
| 146 | |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 147 | static unsigned long mmap_desc(unsigned attr, unsigned long addr_pa, |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 148 | unsigned level) |
| 149 | { |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 150 | unsigned long desc = addr_pa; |
Sandrine Bailleux | 52b1ba6 | 2016-03-01 14:01:03 +0000 | [diff] [blame] | 151 | int mem_type; |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 152 | |
| 153 | desc |= level == 3 ? TABLE_DESC : BLOCK_DESC; |
| 154 | |
| 155 | desc |= attr & MT_NS ? LOWER_ATTRS(NS) : 0; |
| 156 | |
| 157 | desc |= attr & MT_RW ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO); |
| 158 | |
| 159 | desc |= LOWER_ATTRS(ACCESS_FLAG); |
| 160 | |
Sandrine Bailleux | 52b1ba6 | 2016-03-01 14:01:03 +0000 | [diff] [blame] | 161 | mem_type = MT_TYPE(attr); |
| 162 | if (mem_type == MT_MEMORY) { |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 163 | desc |= LOWER_ATTRS(ATTR_IWBWA_OWBWA_NTR_INDEX | ISH); |
| 164 | if (attr & MT_RW) |
| 165 | desc |= UPPER_ATTRS(XN); |
Sandrine Bailleux | 52b1ba6 | 2016-03-01 14:01:03 +0000 | [diff] [blame] | 166 | } else if (mem_type == MT_NON_CACHEABLE) { |
| 167 | desc |= LOWER_ATTRS(ATTR_NON_CACHEABLE_INDEX | OSH); |
| 168 | if (attr & MT_RW) |
| 169 | desc |= UPPER_ATTRS(XN); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 170 | } else { |
Sandrine Bailleux | 52b1ba6 | 2016-03-01 14:01:03 +0000 | [diff] [blame] | 171 | assert(mem_type == MT_DEVICE); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 172 | desc |= LOWER_ATTRS(ATTR_DEVICE_INDEX | OSH); |
| 173 | desc |= UPPER_ATTRS(XN); |
| 174 | } |
| 175 | |
Sandrine Bailleux | 52b1ba6 | 2016-03-01 14:01:03 +0000 | [diff] [blame] | 176 | debug_print((mem_type == MT_MEMORY) ? "MEM" : |
| 177 | ((mem_type == MT_NON_CACHEABLE) ? "NC" : "DEV")); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 178 | debug_print(attr & MT_RW ? "-RW" : "-RO"); |
| 179 | debug_print(attr & MT_NS ? "-NS" : "-S"); |
| 180 | |
| 181 | return desc; |
| 182 | } |
| 183 | |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 184 | static int mmap_region_attr(mmap_region_t *mm, unsigned long base_va, |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 185 | unsigned long size) |
| 186 | { |
| 187 | int attr = mm->attr; |
Sandrine Bailleux | 52b1ba6 | 2016-03-01 14:01:03 +0000 | [diff] [blame] | 188 | int old_mem_type, new_mem_type; |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 189 | |
| 190 | for (;;) { |
| 191 | ++mm; |
| 192 | |
| 193 | if (!mm->size) |
| 194 | return attr; /* Reached end of list */ |
| 195 | |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 196 | if (mm->base_va >= base_va + size) |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 197 | return attr; /* Next region is after area so end */ |
| 198 | |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 199 | if (mm->base_va + mm->size <= base_va) |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 200 | continue; /* Next region has already been overtaken */ |
| 201 | |
| 202 | if ((mm->attr & attr) == attr) |
| 203 | continue; /* Region doesn't override attribs so skip */ |
| 204 | |
Sandrine Bailleux | 52b1ba6 | 2016-03-01 14:01:03 +0000 | [diff] [blame] | 205 | /* |
| 206 | * Update memory mapping attributes in 2 steps: |
| 207 | * 1) Update access permissions and security state flags |
| 208 | * 2) Update memory type. |
| 209 | * |
| 210 | * See xlat_tables.h for details about the attributes priority |
| 211 | * system and the rules dictating whether attributes should be |
| 212 | * updated. |
| 213 | */ |
| 214 | old_mem_type = MT_TYPE(attr); |
| 215 | new_mem_type = MT_TYPE(mm->attr); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 216 | attr &= mm->attr; |
Sandrine Bailleux | 52b1ba6 | 2016-03-01 14:01:03 +0000 | [diff] [blame] | 217 | if (new_mem_type < old_mem_type) |
| 218 | attr = (attr & ~MT_TYPE_MASK) | new_mem_type; |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 219 | |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 220 | if (mm->base_va > base_va || |
| 221 | mm->base_va + mm->size < base_va + size) |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 222 | return -1; /* Region doesn't fully cover our area */ |
| 223 | } |
| 224 | } |
| 225 | |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 226 | static mmap_region_t *init_xlation_table(mmap_region_t *mm, |
| 227 | unsigned long base_va, |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 228 | unsigned long *table, unsigned level) |
| 229 | { |
| 230 | unsigned level_size_shift = L1_XLAT_ADDRESS_SHIFT - (level - 1) * |
| 231 | XLAT_TABLE_ENTRIES_SHIFT; |
| 232 | unsigned level_size = 1 << level_size_shift; |
Lin Ma | 0b9d59f | 2014-05-20 11:25:55 -0700 | [diff] [blame] | 233 | unsigned long level_index_mask = XLAT_TABLE_ENTRIES_MASK << level_size_shift; |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 234 | |
| 235 | assert(level <= 3); |
| 236 | |
| 237 | debug_print("New xlat table:\n"); |
| 238 | |
| 239 | do { |
| 240 | unsigned long desc = UNSET_DESC; |
| 241 | |
Kristina Martsenko | ed0995c | 2016-02-11 18:11:56 +0000 | [diff] [blame] | 242 | if (!mm->size) { |
| 243 | /* Done mapping regions; finish zeroing the table */ |
| 244 | desc = INVALID_DESC; |
| 245 | } else if (mm->base_va + mm->size <= base_va) { |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 246 | /* Area now after the region so skip it */ |
| 247 | ++mm; |
| 248 | continue; |
| 249 | } |
| 250 | |
Soby Mathew | c9bac9c | 2016-01-19 17:52:28 +0000 | [diff] [blame] | 251 | debug_print("%s VA:0x%lx size:0x%x ", get_level_spacer(level), |
| 252 | base_va, level_size); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 253 | |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 254 | if (mm->base_va >= base_va + level_size) { |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 255 | /* Next region is after area so nothing to map yet */ |
| 256 | desc = INVALID_DESC; |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 257 | } else if (mm->base_va <= base_va && mm->base_va + mm->size >= |
| 258 | base_va + level_size) { |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 259 | /* Next region covers all of area */ |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 260 | int attr = mmap_region_attr(mm, base_va, level_size); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 261 | if (attr >= 0) |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 262 | desc = mmap_desc(attr, |
| 263 | base_va - mm->base_va + mm->base_pa, |
| 264 | level); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 265 | } |
| 266 | /* else Next region only partially covers area, so need */ |
| 267 | |
| 268 | if (desc == UNSET_DESC) { |
| 269 | /* Area not covered by a region so need finer table */ |
| 270 | unsigned long *new_table = xlat_tables[next_xlat++]; |
| 271 | assert(next_xlat <= MAX_XLAT_TABLES); |
| 272 | desc = TABLE_DESC | (unsigned long)new_table; |
| 273 | |
| 274 | /* Recurse to fill in new table */ |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 275 | mm = init_xlation_table(mm, base_va, |
| 276 | new_table, level+1); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 277 | } |
| 278 | |
| 279 | debug_print("\n"); |
| 280 | |
| 281 | *table++ = desc; |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame] | 282 | base_va += level_size; |
Kristina Martsenko | ed0995c | 2016-02-11 18:11:56 +0000 | [diff] [blame] | 283 | } while ((base_va & level_index_mask) && (base_va < ADDR_SPACE_SIZE)); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 284 | |
| 285 | return mm; |
| 286 | } |
| 287 | |
Lin Ma | 741a382 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 288 | static unsigned int calc_physical_addr_size_bits(unsigned long max_addr) |
| 289 | { |
| 290 | /* Physical address can't exceed 48 bits */ |
| 291 | assert((max_addr & ADDR_MASK_48_TO_63) == 0); |
| 292 | |
| 293 | /* 48 bits address */ |
| 294 | if (max_addr & ADDR_MASK_44_TO_47) |
| 295 | return TCR_PS_BITS_256TB; |
| 296 | |
| 297 | /* 44 bits address */ |
| 298 | if (max_addr & ADDR_MASK_42_TO_43) |
| 299 | return TCR_PS_BITS_16TB; |
| 300 | |
| 301 | /* 42 bits address */ |
| 302 | if (max_addr & ADDR_MASK_40_TO_41) |
| 303 | return TCR_PS_BITS_4TB; |
| 304 | |
| 305 | /* 40 bits address */ |
| 306 | if (max_addr & ADDR_MASK_36_TO_39) |
| 307 | return TCR_PS_BITS_1TB; |
| 308 | |
| 309 | /* 36 bits address */ |
| 310 | if (max_addr & ADDR_MASK_32_TO_35) |
| 311 | return TCR_PS_BITS_64GB; |
| 312 | |
| 313 | return TCR_PS_BITS_4GB; |
| 314 | } |
| 315 | |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 316 | void init_xlat_tables(void) |
| 317 | { |
| 318 | print_mmap(); |
| 319 | init_xlation_table(mmap, 0, l1_xlation_table, 1); |
Lin Ma | 741a382 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 320 | tcr_ps_bits = calc_physical_addr_size_bits(max_pa); |
| 321 | assert(max_va < ADDR_SPACE_SIZE); |
Jon Medhurst | bb1fe20 | 2014-01-24 15:41:33 +0000 | [diff] [blame] | 322 | } |
Dan Handley | b226a4d | 2014-05-16 14:08:45 +0100 | [diff] [blame] | 323 | |
| 324 | /******************************************************************************* |
| 325 | * Macro generating the code for the function enabling the MMU in the given |
| 326 | * exception level, assuming that the pagetables have already been created. |
| 327 | * |
| 328 | * _el: Exception level at which the function will run |
| 329 | * _tcr_extra: Extra bits to set in the TCR register. This mask will |
| 330 | * be OR'ed with the default TCR value. |
| 331 | * _tlbi_fct: Function to invalidate the TLBs at the current |
| 332 | * exception level |
| 333 | ******************************************************************************/ |
| 334 | #define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \ |
Achin Gupta | e998254 | 2014-06-26 08:59:07 +0100 | [diff] [blame] | 335 | void enable_mmu_el##_el(uint32_t flags) \ |
Dan Handley | b226a4d | 2014-05-16 14:08:45 +0100 | [diff] [blame] | 336 | { \ |
| 337 | uint64_t mair, tcr, ttbr; \ |
| 338 | uint32_t sctlr; \ |
| 339 | \ |
| 340 | assert(IS_IN_EL(_el)); \ |
| 341 | assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \ |
| 342 | \ |
| 343 | /* Set attributes in the right indices of the MAIR */ \ |
| 344 | mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \ |
| 345 | mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \ |
| 346 | ATTR_IWBWA_OWBWA_NTR_INDEX); \ |
Sandrine Bailleux | 52b1ba6 | 2016-03-01 14:01:03 +0000 | [diff] [blame] | 347 | mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, \ |
| 348 | ATTR_NON_CACHEABLE_INDEX); \ |
Dan Handley | b226a4d | 2014-05-16 14:08:45 +0100 | [diff] [blame] | 349 | write_mair_el##_el(mair); \ |
| 350 | \ |
| 351 | /* Invalidate TLBs at the current exception level */ \ |
| 352 | _tlbi_fct(); \ |
| 353 | \ |
| 354 | /* Set TCR bits as well. */ \ |
| 355 | /* Inner & outer WBWA & shareable + T0SZ = 32 */ \ |
| 356 | tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \ |
Lin Ma | 741a382 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 357 | TCR_RGN_INNER_WBA | \ |
| 358 | (64 - __builtin_ctzl(ADDR_SPACE_SIZE)); \ |
Dan Handley | b226a4d | 2014-05-16 14:08:45 +0100 | [diff] [blame] | 359 | tcr |= _tcr_extra; \ |
| 360 | write_tcr_el##_el(tcr); \ |
| 361 | \ |
| 362 | /* Set TTBR bits as well */ \ |
| 363 | ttbr = (uint64_t) l1_xlation_table; \ |
| 364 | write_ttbr0_el##_el(ttbr); \ |
| 365 | \ |
| 366 | /* Ensure all translation table writes have drained */ \ |
| 367 | /* into memory, the TLB invalidation is complete, */ \ |
| 368 | /* and translation register writes are committed */ \ |
| 369 | /* before enabling the MMU */ \ |
| 370 | dsb(); \ |
| 371 | isb(); \ |
| 372 | \ |
| 373 | sctlr = read_sctlr_el##_el(); \ |
Achin Gupta | 9f09835 | 2014-07-18 18:38:28 +0100 | [diff] [blame] | 374 | sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \ |
Achin Gupta | e998254 | 2014-06-26 08:59:07 +0100 | [diff] [blame] | 375 | \ |
| 376 | if (flags & DISABLE_DCACHE) \ |
| 377 | sctlr &= ~SCTLR_C_BIT; \ |
| 378 | else \ |
| 379 | sctlr |= SCTLR_C_BIT; \ |
| 380 | \ |
Dan Handley | b226a4d | 2014-05-16 14:08:45 +0100 | [diff] [blame] | 381 | write_sctlr_el##_el(sctlr); \ |
| 382 | \ |
| 383 | /* Ensure the MMU enable takes effect immediately */ \ |
| 384 | isb(); \ |
| 385 | } |
| 386 | |
| 387 | /* Define EL1 and EL3 variants of the function enabling the MMU */ |
Lin Ma | 741a382 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 388 | DEFINE_ENABLE_MMU_EL(1, |
| 389 | (tcr_ps_bits << TCR_EL1_IPS_SHIFT), |
| 390 | tlbivmalle1) |
| 391 | DEFINE_ENABLE_MMU_EL(3, |
| 392 | TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT), |
| 393 | tlbialle3) |