Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 6 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 7 | #include <asm_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <common/bl_common.h> |
| 9 | #include <common/debug.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 10 | #include <cortex_a53.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
Boyan Karatotev | 5d38cb3 | 2023-01-27 09:37:07 +0000 | [diff] [blame] | 13 | #include <lib/cpus/errata.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 14 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 15 | /* --------------------------------------------- |
| 16 | * Disable L1 data cache and unified L2 cache |
| 17 | * --------------------------------------------- |
| 18 | */ |
| 19 | func cortex_a53_disable_dcache |
Boyan Karatotev | 6ad9725 | 2023-04-05 16:02:34 +0100 | [diff] [blame] | 20 | sysreg_bit_clear sctlr_el3, SCTLR_C_BIT |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 21 | isb |
| 22 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 23 | endfunc cortex_a53_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 24 | |
| 25 | /* --------------------------------------------- |
| 26 | * Disable intra-cluster coherency |
| 27 | * --------------------------------------------- |
| 28 | */ |
| 29 | func cortex_a53_disable_smp |
Boyan Karatotev | 6ad9725 | 2023-04-05 16:02:34 +0100 | [diff] [blame] | 30 | sysreg_bit_clear CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 31 | isb |
| 32 | dsb sy |
| 33 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 34 | endfunc cortex_a53_disable_smp |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 35 | |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 36 | /* Due to the nature of the errata it is applied unconditionally when chosen */ |
Boyan Karatotev | 6ad9725 | 2023-04-05 16:02:34 +0100 | [diff] [blame] | 37 | check_erratum_ls cortex_a53, ERRATUM(819472), CPU_REV(0, 1) |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 38 | /* erratum workaround is interleaved with generic code */ |
| 39 | add_erratum_entry cortex_a53, ERRATUM(819472), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET |
| 40 | |
| 41 | /* Due to the nature of the errata it is applied unconditionally when chosen */ |
Boyan Karatotev | 6ad9725 | 2023-04-05 16:02:34 +0100 | [diff] [blame] | 42 | check_erratum_ls cortex_a53, ERRATUM(824069), CPU_REV(0, 2) |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 43 | /* erratum workaround is interleaved with generic code */ |
| 44 | add_erratum_entry cortex_a53, ERRATUM(824069), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET |
| 45 | |
| 46 | workaround_reset_start cortex_a53, ERRATUM(826319), ERRATA_A53_826319 |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 47 | mrs x1, CORTEX_A53_L2ACTLR_EL1 |
| 48 | bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN |
| 49 | orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH |
| 50 | msr CORTEX_A53_L2ACTLR_EL1, x1 |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 51 | workaround_reset_end cortex_a53, ERRATUM(826319) |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 52 | |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 53 | check_erratum_ls cortex_a53, ERRATUM(826319), CPU_REV(0, 2) |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 54 | |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 55 | /* Due to the nature of the errata it is applied unconditionally when chosen */ |
Boyan Karatotev | 6ad9725 | 2023-04-05 16:02:34 +0100 | [diff] [blame] | 56 | check_erratum_ls cortex_a53, ERRATUM(827319), CPU_REV(0, 2) |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 57 | /* erratum workaround is interleaved with generic code */ |
| 58 | add_erratum_entry cortex_a53, ERRATUM(827319), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET |
| 59 | |
| 60 | check_erratum_custom_start cortex_a53, ERRATUM(835769) |
Boyan Karatotev | 6ad9725 | 2023-04-05 16:02:34 +0100 | [diff] [blame] | 61 | cmp x0, CPU_REV(0, 4) |
Boyan Karatotev | 6f20c7f | 2023-04-03 16:28:10 +0100 | [diff] [blame] | 62 | b.hi errata_not_applies |
| 63 | /* |
| 64 | * Fix potentially available for revisions r0p2, r0p3 and r0p4. |
| 65 | * If r0p2, r0p3 or r0p4; check for fix in REVIDR, else exit. |
| 66 | */ |
| 67 | cmp x0, #0x01 |
| 68 | mov x0, #ERRATA_APPLIES |
| 69 | b.ls exit_check_errata_835769 |
| 70 | /* Load REVIDR. */ |
| 71 | mrs x1, revidr_el1 |
| 72 | /* If REVIDR[7] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ |
| 73 | tbz x1, #7, exit_check_errata_835769 |
| 74 | errata_not_applies: |
| 75 | mov x0, #ERRATA_NOT_APPLIES |
| 76 | exit_check_errata_835769: |
| 77 | ret |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 78 | check_erratum_custom_end cortex_a53, ERRATUM(835769) |
Boyan Karatotev | 6f20c7f | 2023-04-03 16:28:10 +0100 | [diff] [blame] | 79 | |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 80 | /* workaround at build time */ |
| 81 | add_erratum_entry cortex_a53, ERRATUM(835769), ERRATA_A53_835769, NO_APPLY_AT_RESET |
| 82 | |
| 83 | /* |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 84 | * Disable the cache non-temporal hint. |
| 85 | * |
| 86 | * This ignores the Transient allocation hint in the MAIR and treats |
| 87 | * allocations the same as non-transient allocation types. As a result, |
| 88 | * the LDNP and STNP instructions in AArch64 behave the same as the |
| 89 | * equivalent LDP and STP instructions. |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 90 | */ |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 91 | workaround_reset_start cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT |
Boyan Karatotev | 6ad9725 | 2023-04-05 16:02:34 +0100 | [diff] [blame] | 92 | sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_DTAH |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 93 | workaround_reset_end cortex_a53, ERRATUM(836870) |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 94 | |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 95 | check_erratum_ls cortex_a53, ERRATUM(836870), CPU_REV(0, 3) |
Boyan Karatotev | 6f20c7f | 2023-04-03 16:28:10 +0100 | [diff] [blame] | 96 | |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 97 | check_erratum_custom_start cortex_a53, ERRATUM(843419) |
Boyan Karatotev | 6f20c7f | 2023-04-03 16:28:10 +0100 | [diff] [blame] | 98 | mov x1, #ERRATA_APPLIES |
| 99 | mov x2, #ERRATA_NOT_APPLIES |
Boyan Karatotev | 6ad9725 | 2023-04-05 16:02:34 +0100 | [diff] [blame] | 100 | cmp x0, CPU_REV(0, 4) |
Boyan Karatotev | 6f20c7f | 2023-04-03 16:28:10 +0100 | [diff] [blame] | 101 | csel x0, x1, x2, ls |
| 102 | /* |
| 103 | * Fix potentially available for revision r0p4. |
| 104 | * If r0p4 check for fix in REVIDR, else exit. |
| 105 | */ |
| 106 | b.ne exit_check_errata_843419 |
| 107 | /* Load REVIDR. */ |
| 108 | mrs x3, revidr_el1 |
| 109 | /* If REVIDR[8] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ |
| 110 | tbz x3, #8, exit_check_errata_843419 |
| 111 | mov x0, x2 |
| 112 | exit_check_errata_843419: |
| 113 | ret |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 114 | check_erratum_custom_end cortex_a53, ERRATUM(843419) |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 115 | |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 116 | /* workaround at build time */ |
| 117 | add_erratum_entry cortex_a53, ERRATUM(843419), ERRATA_A53_843419, NO_APPLY_AT_RESET |
| 118 | |
| 119 | /* |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 120 | * Earlier revisions of the core are affected as well, but don't |
| 121 | * have the chicken bit in the CPUACTLR register. It is expected that |
| 122 | * the rich OS takes care of that, especially as the workaround is |
| 123 | * shared with other erratas in those revisions of the CPU. |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 124 | */ |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 125 | workaround_reset_start cortex_a53, ERRATUM(855873), ERRATA_A53_855873 |
Boyan Karatotev | 6ad9725 | 2023-04-05 16:02:34 +0100 | [diff] [blame] | 126 | sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_ENDCCASCI |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 127 | workaround_reset_end cortex_a53, ERRATUM(855873) |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 128 | |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 129 | check_erratum_hs cortex_a53, ERRATUM(855873), CPU_REV(0, 3) |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 130 | |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 131 | check_erratum_chosen cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 132 | |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 133 | /* erratum has no workaround in the cpu. Generic code must take care */ |
| 134 | add_erratum_entry cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924, NO_APPLY_AT_RESET |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 135 | |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 136 | cpu_reset_func_start cortex_a53 |
Boyan Karatotev | 6ad9725 | 2023-04-05 16:02:34 +0100 | [diff] [blame] | 137 | /* Enable the SMP bit. */ |
| 138 | sysreg_bit_set CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 139 | cpu_reset_func_end cortex_a53 |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 140 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 141 | func cortex_a53_core_pwr_dwn |
| 142 | mov x18, x30 |
| 143 | |
| 144 | /* --------------------------------------------- |
| 145 | * Turn off caches. |
| 146 | * --------------------------------------------- |
| 147 | */ |
| 148 | bl cortex_a53_disable_dcache |
| 149 | |
| 150 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 151 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 152 | * --------------------------------------------- |
| 153 | */ |
| 154 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 155 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 156 | |
| 157 | /* --------------------------------------------- |
| 158 | * Come out of intra cluster coherency |
| 159 | * --------------------------------------------- |
| 160 | */ |
| 161 | mov x30, x18 |
| 162 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 163 | endfunc cortex_a53_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 164 | |
| 165 | func cortex_a53_cluster_pwr_dwn |
| 166 | mov x18, x30 |
| 167 | |
| 168 | /* --------------------------------------------- |
| 169 | * Turn off caches. |
| 170 | * --------------------------------------------- |
| 171 | */ |
| 172 | bl cortex_a53_disable_dcache |
| 173 | |
| 174 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 175 | * Flush L1 caches. |
| 176 | * --------------------------------------------- |
| 177 | */ |
| 178 | mov x0, #DCCISW |
| 179 | bl dcsw_op_level1 |
| 180 | |
| 181 | /* --------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 182 | * Disable the optional ACP. |
| 183 | * --------------------------------------------- |
| 184 | */ |
| 185 | bl plat_disable_acp |
| 186 | |
| 187 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 188 | * Flush L2 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 189 | * --------------------------------------------- |
| 190 | */ |
| 191 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 192 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 193 | |
| 194 | /* --------------------------------------------- |
| 195 | * Come out of intra cluster coherency |
| 196 | * --------------------------------------------- |
| 197 | */ |
| 198 | mov x30, x18 |
| 199 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 200 | endfunc cortex_a53_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 201 | |
Boyan Karatotev | a6c9cf7 | 2023-04-04 11:30:32 +0100 | [diff] [blame] | 202 | errata_report_shim cortex_a53 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 203 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 204 | /* --------------------------------------------- |
| 205 | * This function provides cortex_a53 specific |
| 206 | * register information for crash reporting. |
| 207 | * It needs to return with x6 pointing to |
| 208 | * a list of register names in ascii and |
| 209 | * x8 - x15 having values of registers to be |
| 210 | * reported. |
| 211 | * --------------------------------------------- |
| 212 | */ |
| 213 | .section .rodata.cortex_a53_regs, "aS" |
| 214 | cortex_a53_regs: /* The ascii list of register names to be reported */ |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 215 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ |
| 216 | "cpuactlr_el1", "" |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 217 | |
| 218 | func cortex_a53_cpu_reg_dump |
| 219 | adr x6, cortex_a53_regs |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 220 | mrs x8, CORTEX_A53_ECTLR_EL1 |
| 221 | mrs x9, CORTEX_A53_MERRSR_EL1 |
| 222 | mrs x10, CORTEX_A53_L2MERRSR_EL1 |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 223 | mrs x11, CORTEX_A53_CPUACTLR_EL1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 224 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 225 | endfunc cortex_a53_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 226 | |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 227 | declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ |
| 228 | cortex_a53_reset_func, \ |
| 229 | cortex_a53_core_pwr_dwn, \ |
| 230 | cortex_a53_cluster_pwr_dwn |