| Yann Gautier | 7511539 | 2018-07-16 14:49:34 +0200 | [diff] [blame] | 1 | Trusted Firmware-A for STM32MP1 |
| 2 | =============================== |
| 3 | |
| 4 | STM32MP1 is a microprocessor designed by STMicroelectronics |
| 5 | based on a dual Arm Cortex-A7. |
| 6 | It is an Armv7-A platform, using dedicated code from TF-A. |
| 7 | |
| 8 | |
| 9 | Design |
| 10 | ------ |
| 11 | The STM32MP1 resets in the ROM code of the Cortex-A7. |
| 12 | The primary boot core (core 0) executes the boot sequence while |
| 13 | secondary boot core (core 1) is kept in a holding pen loop. |
| 14 | The ROM code boot sequence loads the TF-A binary image from boot device |
| 15 | to embedded SRAM. |
| 16 | |
| 17 | The TF-A image must be properly formatted with a STM32 header structure |
| 18 | for ROM code is able to load this image. |
| 19 | Tool stm32image can be used to prepend this header to the generated TF-A binary. |
| 20 | |
| 21 | At compilation step, BL2, BL32 and DTB file are linked together in a single |
| 22 | binary. The stm32image tool is also generated and the header is added to TF-A |
| 23 | binary. This binary file with header is named tf-a-stm32mp157c-ev1.stm32. |
| 24 | It can then be copied in the first partition of the boot device. |
| 25 | |
| 26 | |
| 27 | Memory mapping |
| 28 | ~~~~~~~~~~~~~~ |
| 29 | |
| 30 | :: |
| 31 | |
| 32 | 0x00000000 +-----------------+ |
| 33 | | | ROM |
| 34 | 0x00020000 +-----------------+ |
| 35 | | | |
| 36 | | ... | |
| 37 | | | |
| 38 | 0x2FFC0000 +-----------------+ \ |
| 39 | | | | |
| 40 | | ... | | |
| 41 | | | | |
| 42 | 0x2FFD8000 +-----------------+ | |
| 43 | | TF-A DTB | | Embedded SRAM |
| 44 | 0x2FFDC000 +-----------------+ | |
| 45 | | BL2 | | |
| 46 | 0x2FFEF000 +-----------------+ | |
| 47 | | BL32 | | |
| 48 | 0x30000000 +-----------------+ / |
| 49 | | | |
| 50 | | ... | |
| 51 | | | |
| 52 | 0x40000000 +-----------------+ |
| 53 | | | |
| 54 | | | Devices |
| 55 | | | |
| 56 | 0xC0000000 +-----------------+ \ |
| 57 | | | | |
| 58 | 0xC0100000 +-----------------+ | |
| 59 | | BL33 | | Non-secure RAM (DDR) |
| 60 | | ... | | |
| 61 | | | | |
| 62 | 0xFFFFFFFF +-----------------+ / |
| 63 | |
| 64 | |
| 65 | Boot sequence |
| 66 | ~~~~~~~~~~~~~ |
| 67 | |
| 68 | ROM code -> BL2 (compiled with BL2_AT_EL3) -> BL32 (SP_min) -> BL33 (U-Boot) |
| 69 | |
| 70 | |
| 71 | Build Instructions |
| 72 | ------------------ |
| 73 | |
| 74 | To build: |
| 75 | |
| 76 | .. code:: bash |
| 77 | |
| 78 | make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 AARCH32_SP=sp_min |
| 79 | |
| 80 | The following build options are supported: |
| 81 | |
| 82 | - ``ENABLE_STACK_PROTECTOR``: To enable the stack protection. |