Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 1 | /* |
Chandni Cherukuri | c873efc | 2023-02-16 20:22:32 +0530 | [diff] [blame] | 2 | * Copyright (c) 2020-2023, Arm Limited. All rights reserved. |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <plat/arm/board/common/v2m_def.h> |
| 11 | #include <plat/arm/common/arm_def.h> |
| 12 | #include <plat/arm/css/common/css_def.h> |
| 13 | |
| 14 | /* UART related constants */ |
| 15 | #define PLAT_ARM_BOOT_UART_BASE ULL(0x2A400000) |
| 16 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ U(50000000) |
| 17 | |
Chandni Cherukuri | 118ad71 | 2021-12-02 11:22:59 +0530 | [diff] [blame] | 18 | /* IOFPGA UART0 */ |
| 19 | #define PLAT_ARM_RUN_UART_BASE ULL(0x1C090000) |
| 20 | #define PLAT_ARM_RUN_UART_CLK_IN_HZ U(24000000) |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 21 | |
| 22 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE |
| 23 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ |
| 24 | |
| 25 | #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) |
| 26 | #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000) |
| 27 | |
Manoj Kumar | 5887612 | 2021-01-10 16:12:24 +0000 | [diff] [blame] | 28 | #define MAX_IO_DEVICES U(3) |
| 29 | #define MAX_IO_HANDLES U(4) |
| 30 | |
| 31 | #define PLAT_ARM_FLASH_IMAGE_BASE ULL(0x1A000000) |
| 32 | #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE ULL(0x01000000) |
| 33 | |
| 34 | #define PLAT_ARM_NVM_BASE ULL(0x1A000000) |
| 35 | #define PLAT_ARM_NVM_SIZE ULL(0x01000000) |
| 36 | |
| 37 | #if defined NS_BL1U_BASE |
| 38 | #undef NS_BL1U_BASE |
| 39 | #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x00800000)) |
| 40 | #endif |
| 41 | |
| 42 | /* |
| 43 | * There are no non-volatile counters in morello, these macros points |
| 44 | * to unused addresses. |
| 45 | */ |
| 46 | #define SOC_TRUSTED_NVCTR_BASE ULL(0x7FE70000) |
| 47 | #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + U(0x0000)) |
| 48 | #define TFW_NVCTR_SIZE U(4) |
| 49 | #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + U(0x0004)) |
| 50 | #define NTFW_CTR_SIZE U(4) |
| 51 | |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 52 | /* |
| 53 | * To access the complete DDR memory along with remote chip's DDR memory, |
| 54 | * which is at 4 TB offset, physical and virtual address space limits are |
| 55 | * extended to 43-bits. |
| 56 | */ |
| 57 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43) |
| 58 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43) |
| 59 | |
| 60 | #if CSS_USE_SCMI_SDS_DRIVER |
| 61 | #define MORELLO_SCMI_PAYLOAD_BASE ULL(0x45400000) |
| 62 | #else |
| 63 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE ULL(0x45400000) |
| 64 | #endif |
| 65 | |
| 66 | #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00080000) |
Manoj Kumar | 5887612 | 2021-01-10 16:12:24 +0000 | [diff] [blame] | 67 | |
| 68 | /* |
| 69 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 70 | * plus a little space for growth. |
| 71 | */ |
| 72 | #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) |
| 73 | |
| 74 | /* |
| 75 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 76 | */ |
| 77 | |
| 78 | #if USE_ROMLIB |
| 79 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) |
| 80 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xE000) |
| 81 | #else |
| 82 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0) |
| 83 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0) |
| 84 | #endif |
| 85 | |
| 86 | /* |
| 87 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 88 | * little space for growth. |
| 89 | */ |
| 90 | #if TRUSTED_BOARD_BOOT |
| 91 | # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) |
| 92 | #else |
| 93 | # define PLAT_ARM_MAX_BL2_SIZE UL(0x14000) |
| 94 | #endif |
| 95 | |
| 96 | #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 97 | |
| 98 | /******************************************************************************* |
| 99 | * MORELLO topology related constants |
| 100 | ******************************************************************************/ |
| 101 | #define MORELLO_MAX_CPUS_PER_CLUSTER U(2) |
| 102 | #define PLAT_ARM_CLUSTER_COUNT U(2) |
| 103 | #define PLAT_MORELLO_CHIP_COUNT U(1) |
| 104 | #define MORELLO_MAX_CLUSTERS_PER_CHIP U(2) |
| 105 | #define MORELLO_MAX_PE_PER_CPU U(1) |
| 106 | |
| 107 | #define PLATFORM_CORE_COUNT (PLAT_MORELLO_CHIP_COUNT * \ |
| 108 | PLAT_ARM_CLUSTER_COUNT * \ |
| 109 | MORELLO_MAX_CPUS_PER_CLUSTER * \ |
| 110 | MORELLO_MAX_PE_PER_CPU) |
| 111 | |
| 112 | /* System power domain level */ |
| 113 | #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 |
| 114 | |
| 115 | /* |
| 116 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 117 | * plat_arm_mmap array defined for each BL stage. |
| 118 | */ |
Manoj Kumar | 5887612 | 2021-01-10 16:12:24 +0000 | [diff] [blame] | 119 | #if IMAGE_BL1 || IMAGE_BL31 |
| 120 | # define PLAT_ARM_MMAP_ENTRIES U(6) |
| 121 | # define MAX_XLAT_TABLES U(7) |
| 122 | #else |
| 123 | # define PLAT_ARM_MMAP_ENTRIES U(5) |
| 124 | # define MAX_XLAT_TABLES U(6) |
| 125 | #endif |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 126 | |
Manoj Kumar | 5887612 | 2021-01-10 16:12:24 +0000 | [diff] [blame] | 127 | /* |
| 128 | * Size of cacheable stacks |
| 129 | */ |
| 130 | #if defined(IMAGE_BL1) |
| 131 | # if TRUSTED_BOARD_BOOT |
| 132 | # define PLATFORM_STACK_SIZE UL(0x1000) |
| 133 | # else |
| 134 | # define PLATFORM_STACK_SIZE UL(0x440) |
| 135 | # endif |
| 136 | #elif defined(IMAGE_BL2) |
| 137 | # if TRUSTED_BOARD_BOOT |
| 138 | # define PLATFORM_STACK_SIZE UL(0x1000) |
| 139 | # else |
| 140 | # define PLATFORM_STACK_SIZE UL(0x400) |
| 141 | # endif |
| 142 | #elif defined(IMAGE_BL2U) |
| 143 | # define PLATFORM_STACK_SIZE UL(0x400) |
| 144 | #elif defined(IMAGE_BL31) |
| 145 | # if SPM_MM |
| 146 | # define PLATFORM_STACK_SIZE UL(0x500) |
| 147 | # else |
| 148 | # define PLATFORM_STACK_SIZE UL(0x400) |
| 149 | # endif |
| 150 | #elif defined(IMAGE_BL32) |
| 151 | # define PLATFORM_STACK_SIZE UL(0x440) |
| 152 | #endif |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 153 | |
| 154 | #define PLAT_ARM_NSTIMER_FRAME_ID U(0) |
Manoj Kumar | 5887612 | 2021-01-10 16:12:24 +0000 | [diff] [blame] | 155 | |
| 156 | #define PLAT_ARM_TRUSTED_ROM_BASE U(0x0) |
| 157 | #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) /* 128KB */ |
| 158 | |
| 159 | #define PLAT_ARM_NSRAM_BASE ULL(0x06000000) |
| 160 | #define PLAT_ARM_NSRAM_SIZE UL(0x00010000) /* 64KB */ |
| 161 | |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 162 | #define PLAT_CSS_MHU_BASE UL(0x45000000) |
| 163 | #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE |
| 164 | #define PLAT_MAX_PWR_LVL U(2) |
| 165 | |
| 166 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) |
| 167 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 168 | |
| 169 | #define MORELLO_DEVICE_BASE ULL(0x08000000) |
| 170 | #define MORELLO_DEVICE_SIZE ULL(0x48000000) |
| 171 | |
Manoj Kumar | 5887612 | 2021-01-10 16:12:24 +0000 | [diff] [blame] | 172 | /*Secure Watchdog Constants */ |
| 173 | #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) |
| 174 | #define SBSA_SECURE_WDOG_TIMEOUT UL(1000) |
| 175 | |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 176 | #define MORELLO_MAP_DEVICE MAP_REGION_FLAT( \ |
| 177 | MORELLO_DEVICE_BASE, \ |
| 178 | MORELLO_DEVICE_SIZE, \ |
| 179 | MT_DEVICE | MT_RW | MT_SECURE) |
| 180 | |
| 181 | #define ARM_MAP_DRAM1 MAP_REGION_FLAT( \ |
| 182 | ARM_DRAM1_BASE, \ |
| 183 | ARM_DRAM1_SIZE, \ |
| 184 | MT_MEMORY | MT_RW | MT_NS) |
| 185 | |
| 186 | /* GIC related constants */ |
| 187 | #define PLAT_ARM_GICD_BASE UL(0x30000000) |
| 188 | #define PLAT_ARM_GICC_BASE UL(0x2C000000) |
| 189 | #define PLAT_ARM_GICR_BASE UL(0x300C0000) |
| 190 | |
Chandni Cherukuri | c5a0c37 | 2020-10-01 10:11:44 +0530 | [diff] [blame] | 191 | /* Number of SCMI channels on the platform */ |
| 192 | #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) |
| 193 | |
Chandni Cherukuri | c873efc | 2023-02-16 20:22:32 +0530 | [diff] [blame] | 194 | /* Platform ID address */ |
| 195 | #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) |
| 196 | |
Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 197 | #endif /* PLATFORM_DEF_H */ |