blob: 402e5e19632969b0d42da9011053697af63833e1 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handleybe234f92014-08-04 16:11:15 +01007#include <arch.h>
8#include <assert.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01009#include <cci400.h>
Vikram Kanigiri40d468c2014-12-23 01:00:22 +000010#include <debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010011#include <mmio.h>
Juan Castillo7f1f0622014-09-09 09:49:23 +010012#include <stdint.h>
Dan Handleybe234f92014-08-04 16:11:15 +010013
14#define MAX_CLUSTERS 2
15
Juan Castillo7f1f0622014-09-09 09:49:23 +010016static uintptr_t cci_base_addr;
Dan Handleybe234f92014-08-04 16:11:15 +010017static unsigned int cci_cluster_ix_to_iface[MAX_CLUSTERS];
18
19
Juan Castillo7f1f0622014-09-09 09:49:23 +010020void cci_init(uintptr_t cci_base,
Dan Handleybe234f92014-08-04 16:11:15 +010021 int slave_iface3_cluster_ix,
22 int slave_iface4_cluster_ix)
23{
24 /*
25 * Check the passed arguments are valid. The cluster indices must be
26 * less than MAX_CLUSTERS, not the same as each other and at least one
Sandrine Bailleux18e785f2015-10-02 08:51:17 +010027 * of them must refer to a valid cluster index.
Dan Handleybe234f92014-08-04 16:11:15 +010028 */
29 assert(cci_base);
30 assert(slave_iface3_cluster_ix < MAX_CLUSTERS);
31 assert(slave_iface4_cluster_ix < MAX_CLUSTERS);
32 assert(slave_iface3_cluster_ix != slave_iface4_cluster_ix);
33 assert((slave_iface3_cluster_ix >= 0) ||
Sandrine Bailleux18e785f2015-10-02 08:51:17 +010034 (slave_iface4_cluster_ix >= 0));
Dan Handleybe234f92014-08-04 16:11:15 +010035
Vikram Kanigiri40d468c2014-12-23 01:00:22 +000036 WARN("Please migrate to common cci driver, This driver will be" \
37 " deprecated in future\n");
38
Dan Handleybe234f92014-08-04 16:11:15 +010039 cci_base_addr = cci_base;
40 if (slave_iface3_cluster_ix >= 0)
41 cci_cluster_ix_to_iface[slave_iface3_cluster_ix] =
42 SLAVE_IFACE3_OFFSET;
43 if (slave_iface4_cluster_ix >= 0)
44 cci_cluster_ix_to_iface[slave_iface4_cluster_ix] =
45 SLAVE_IFACE4_OFFSET;
46}
Achin Gupta4f6ad662013-10-25 09:08:21 +010047
48static inline unsigned long get_slave_iface_base(unsigned long mpidr)
49{
Dan Handleybe234f92014-08-04 16:11:15 +010050 /*
51 * We assume the TF topology code allocates affinity instances
52 * consecutively from zero.
53 * It is a programming error if this is called without initializing
54 * the slave interface to use for this cluster.
55 */
56 unsigned int cluster_id =
57 (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
58
59 assert(cluster_id < MAX_CLUSTERS);
60 assert(cci_cluster_ix_to_iface[cluster_id] != 0);
61
62 return cci_base_addr + cci_cluster_ix_to_iface[cluster_id];
Achin Gupta4f6ad662013-10-25 09:08:21 +010063}
64
Dan Handleybe234f92014-08-04 16:11:15 +010065void cci_enable_cluster_coherency(unsigned long mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010066{
Dan Handleybe234f92014-08-04 16:11:15 +010067 assert(cci_base_addr);
Achin Gupta4f6ad662013-10-25 09:08:21 +010068 /* Enable Snoops and DVM messages */
69 mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG,
70 DVM_EN_BIT | SNOOP_EN_BIT);
71
72 /* Wait for the dust to settle down */
Dan Handleybe234f92014-08-04 16:11:15 +010073 while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT)
Dan Handleya70615f2014-04-09 12:48:25 +010074 ;
Achin Gupta4f6ad662013-10-25 09:08:21 +010075}
76
Dan Handleybe234f92014-08-04 16:11:15 +010077void cci_disable_cluster_coherency(unsigned long mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010078{
Dan Handleybe234f92014-08-04 16:11:15 +010079 assert(cci_base_addr);
Achin Gupta4f6ad662013-10-25 09:08:21 +010080 /* Disable Snoops and DVM messages */
81 mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG,
82 ~(DVM_EN_BIT | SNOOP_EN_BIT));
83
84 /* Wait for the dust to settle down */
Dan Handleybe234f92014-08-04 16:11:15 +010085 while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT)
Dan Handleya70615f2014-04-09 12:48:25 +010086 ;
Achin Gupta4f6ad662013-10-25 09:08:21 +010087}
88