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Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Soby Mathewa0fedc42016-06-16 14:52:04 +01002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __GICV3_H__
32#define __GICV3_H__
33
34/*******************************************************************************
35 * GICv3 miscellaneous definitions
36 ******************************************************************************/
37/* Interrupt group definitions */
Soby Mathew5c5c36b2015-12-03 14:12:54 +000038#define INTR_GROUP1S 0
39#define INTR_GROUP0 1
40#define INTR_GROUP1NS 2
Achin Gupta92712a52015-09-03 14:18:02 +010041
42/* Interrupt IDs reported by the HPPIR and IAR registers */
43#define PENDING_G1S_INTID 1020
44#define PENDING_G1NS_INTID 1021
45
46/* Constant to categorize LPI interrupt */
47#define MIN_LPI_ID 8192
48
49/*******************************************************************************
50 * GICv3 specific Distributor interface register offsets and constants.
51 ******************************************************************************/
52#define GICD_STATUSR 0x10
53#define GICD_SETSPI_NSR 0x40
54#define GICD_CLRSPI_NSR 0x48
55#define GICD_SETSPI_SR 0x50
56#define GICD_CLRSPI_SR 0x50
57#define GICD_IGRPMODR 0xd00
Soby Mathewaaf71c82016-07-26 17:46:56 +010058/*
59 * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and
60 * n >= 32, making the effective offset as 0x6100.
61 */
62#define GICD_IROUTER 0x6000
Achin Gupta92712a52015-09-03 14:18:02 +010063#define GICD_PIDR2_GICV3 0xffe8
64
65#define IGRPMODR_SHIFT 5
66
67/* GICD_CTLR bit definitions */
68#define CTLR_ENABLE_G1NS_SHIFT 1
69#define CTLR_ENABLE_G1S_SHIFT 2
70#define CTLR_ARE_S_SHIFT 4
71#define CTLR_ARE_NS_SHIFT 5
72#define CTLR_DS_SHIFT 6
73#define CTLR_E1NWF_SHIFT 7
74#define GICD_CTLR_RWP_SHIFT 31
75
76#define CTLR_ENABLE_G1NS_MASK 0x1
77#define CTLR_ENABLE_G1S_MASK 0x1
78#define CTLR_ARE_S_MASK 0x1
79#define CTLR_ARE_NS_MASK 0x1
80#define CTLR_DS_MASK 0x1
81#define CTLR_E1NWF_MASK 0x1
82#define GICD_CTLR_RWP_MASK 0x1
83
84#define CTLR_ENABLE_G1NS_BIT (1 << CTLR_ENABLE_G1NS_SHIFT)
85#define CTLR_ENABLE_G1S_BIT (1 << CTLR_ENABLE_G1S_SHIFT)
86#define CTLR_ARE_S_BIT (1 << CTLR_ARE_S_SHIFT)
87#define CTLR_ARE_NS_BIT (1 << CTLR_ARE_NS_SHIFT)
88#define CTLR_DS_BIT (1 << CTLR_DS_SHIFT)
89#define CTLR_E1NWF_BIT (1 << CTLR_E1NWF_SHIFT)
90#define GICD_CTLR_RWP_BIT (1 << GICD_CTLR_RWP_SHIFT)
91
92/* GICD_IROUTER shifts and masks */
93#define IROUTER_IRM_SHIFT 31
94#define IROUTER_IRM_MASK 0x1
95
96/*******************************************************************************
97 * GICv3 Re-distributor interface registers & constants
98 ******************************************************************************/
99#define GICR_PCPUBASE_SHIFT 0x11
100#define GICR_SGIBASE_OFFSET (1 << 0x10) /* 64 KB */
101#define GICR_CTLR 0x0
102#define GICR_TYPER 0x08
103#define GICR_WAKER 0x14
104#define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + 0x80)
105#define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + 0x100)
106#define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + 0x180)
107#define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + 0x400)
108#define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + 0xc00)
109#define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + 0xc04)
110#define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + 0xd00)
111
112/* GICR_CTLR bit definitions */
113#define GICR_CTLR_RWP_SHIFT 3
114#define GICR_CTLR_RWP_MASK 0x1
115#define GICR_CTLR_RWP_BIT (1 << GICR_CTLR_RWP_SHIFT)
116
117/* GICR_WAKER bit definitions */
118#define WAKER_CA_SHIFT 2
119#define WAKER_PS_SHIFT 1
120
121#define WAKER_CA_MASK 0x1
122#define WAKER_PS_MASK 0x1
123
124#define WAKER_CA_BIT (1 << WAKER_CA_SHIFT)
125#define WAKER_PS_BIT (1 << WAKER_PS_SHIFT)
126
127/* GICR_TYPER bit definitions */
128#define TYPER_AFF_VAL_SHIFT 32
129#define TYPER_PROC_NUM_SHIFT 8
130#define TYPER_LAST_SHIFT 4
131
132#define TYPER_AFF_VAL_MASK 0xffffffff
133#define TYPER_PROC_NUM_MASK 0xffff
134#define TYPER_LAST_MASK 0x1
135
136#define TYPER_LAST_BIT (1 << TYPER_LAST_SHIFT)
137
138/*******************************************************************************
139 * GICv3 CPU interface registers & constants
140 ******************************************************************************/
141/* ICC_SRE bit definitions*/
142#define ICC_SRE_EN_BIT (1 << 3)
143#define ICC_SRE_DIB_BIT (1 << 2)
144#define ICC_SRE_DFB_BIT (1 << 1)
145#define ICC_SRE_SRE_BIT (1 << 0)
146
147/* ICC_IGRPEN1_EL3 bit definitions */
148#define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0
149#define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1
150
151#define IGRPEN1_EL3_ENABLE_G1NS_BIT (1 << IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
152#define IGRPEN1_EL3_ENABLE_G1S_BIT (1 << IGRPEN1_EL3_ENABLE_G1S_SHIFT)
153
154/* ICC_IGRPEN0_EL1 bit definitions */
155#define IGRPEN1_EL1_ENABLE_G0_SHIFT 0
156#define IGRPEN1_EL1_ENABLE_G0_BIT (1 << IGRPEN1_EL1_ENABLE_G0_SHIFT)
157
158/* ICC_HPPIR0_EL1 bit definitions */
159#define HPPIR0_EL1_INTID_SHIFT 0
160#define HPPIR0_EL1_INTID_MASK 0xffffff
161
162/* ICC_HPPIR1_EL1 bit definitions */
163#define HPPIR1_EL1_INTID_SHIFT 0
164#define HPPIR1_EL1_INTID_MASK 0xffffff
165
166/* ICC_IAR0_EL1 bit definitions */
167#define IAR0_EL1_INTID_SHIFT 0
168#define IAR0_EL1_INTID_MASK 0xffffff
169
170/* ICC_IAR1_EL1 bit definitions */
171#define IAR1_EL1_INTID_SHIFT 0
172#define IAR1_EL1_INTID_MASK 0xffffff
173
174#ifndef __ASSEMBLY__
175
176#include <stdint.h>
Soby Mathewa0fedc42016-06-16 14:52:04 +0100177#include <types.h>
Achin Gupta92712a52015-09-03 14:18:02 +0100178
179#define gicv3_is_intr_id_special_identifier(id) \
180 (((id) >= PENDING_G1S_INTID) && ((id) <= GIC_SPURIOUS_INTERRUPT))
181
182/*******************************************************************************
183 * Helper GICv3 macros for SEL1
184 ******************************************************************************/
185#define gicv3_acknowledge_interrupt_sel1() read_icc_iar1_el1() &\
186 IAR1_EL1_INTID_MASK
187#define gicv3_get_pending_interrupt_id_sel1() read_icc_hppir1_el1() &\
188 HPPIR1_EL1_INTID_MASK
189#define gicv3_end_of_interrupt_sel1(id) write_icc_eoir1_el1(id)
190
191
192/*******************************************************************************
193 * Helper GICv3 macros for EL3
194 ******************************************************************************/
195#define gicv3_acknowledge_interrupt() read_icc_iar0_el1() &\
196 IAR0_EL1_INTID_MASK
197#define gicv3_end_of_interrupt(id) write_icc_eoir0_el1(id)
198
199/*******************************************************************************
200 * This structure describes some of the implementation defined attributes of the
201 * GICv3 IP. It is used by the platform port to specify these attributes in order
202 * to initialise the GICV3 driver. The attributes are described below.
203 *
204 * 1. The 'gicd_base' field contains the base address of the Distributor
205 * interface programmer's view.
206 *
207 * 2. The 'gicr_base' field contains the base address of the Re-distributor
208 * interface programmer's view.
209 *
210 * 3. The 'g0_interrupt_array' field is a ponter to an array in which each
211 * entry corresponds to an ID of a Group 0 interrupt.
212 *
213 * 4. The 'g0_interrupt_num' field contains the number of entries in the
214 * 'g0_interrupt_array'.
215 *
216 * 5. The 'g1s_interrupt_array' field is a ponter to an array in which each
217 * entry corresponds to an ID of a Group 1 interrupt.
218 *
219 * 6. The 'g1s_interrupt_num' field contains the number of entries in the
220 * 'g1s_interrupt_array'.
221 *
222 * 7. The 'rdistif_num' field contains the number of Redistributor interfaces
223 * the GIC implements. This is equal to the number of CPUs or CPU interfaces
224 * instantiated in the GIC.
225 *
226 * 8. The 'rdistif_base_addrs' field is a pointer to an array that has an entry
227 * for storing the base address of the Redistributor interface frame of each
228 * CPU in the system. The size of the array = 'rdistif_num'. The base
229 * addresses are detected during driver initialisation.
230 *
231 * 9. The 'mpidr_to_core_pos' field is a pointer to a hash function which the
232 * driver will use to convert an MPIDR value to a linear core index. This
233 * index will be used for accessing the 'rdistif_base_addrs' array. This is
234 * an optional field. A GICv3 implementation maps each MPIDR to a linear core
235 * index as well. This mapping can be found by reading the "Affinity Value"
236 * and "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the
237 * "Processor Numbers" are suitable to index into an array to access core
238 * specific information. If this not the case, the platform port must provide
239 * a hash function. Otherwise, the "Processor Number" field will be used to
240 * access the array elements.
241 ******************************************************************************/
Soby Mathewa0fedc42016-06-16 14:52:04 +0100242typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr);
Achin Gupta92712a52015-09-03 14:18:02 +0100243
244typedef struct gicv3_driver_data {
245 uintptr_t gicd_base;
246 uintptr_t gicr_base;
247 unsigned int g0_interrupt_num;
248 unsigned int g1s_interrupt_num;
249 const unsigned int *g0_interrupt_array;
250 const unsigned int *g1s_interrupt_array;
251 unsigned int rdistif_num;
252 uintptr_t *rdistif_base_addrs;
253 mpidr_hash_fn mpidr_to_core_pos;
254} gicv3_driver_data_t;
255
256/*******************************************************************************
257 * GICv3 EL3 driver API
258 ******************************************************************************/
259void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data);
260void gicv3_distif_init(void);
261void gicv3_rdistif_init(unsigned int proc_num);
Jeenu Viswambharan76647d52016-12-09 11:03:15 +0000262void gicv3_rdistif_on(unsigned int proc_num);
263void gicv3_rdistif_off(unsigned int proc_num);
Achin Gupta92712a52015-09-03 14:18:02 +0100264void gicv3_cpuif_enable(unsigned int proc_num);
265void gicv3_cpuif_disable(unsigned int proc_num);
266unsigned int gicv3_get_pending_interrupt_type(void);
267unsigned int gicv3_get_pending_interrupt_id(void);
268unsigned int gicv3_get_interrupt_type(unsigned int id,
269 unsigned int proc_num);
270
271
272#endif /* __ASSEMBLY__ */
273#endif /* __GICV3_H__ */