Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Soby Mathew | 7c6df5b | 2018-01-15 14:43:42 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | #ifndef __ARM_DEF_H__ |
| 7 | #define __ARM_DEF_H__ |
| 8 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 9 | #include <arch.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 10 | #include <common_def.h> |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 11 | #include <gic_common.h> |
| 12 | #include <interrupt_props.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 13 | #include <platform_def.h> |
Juan Castillo | 9b265a8 | 2015-05-07 14:52:44 +0100 | [diff] [blame] | 14 | #include <tbbr_img_def.h> |
Scott Branden | bf404c0 | 2017-04-10 11:45:52 -0700 | [diff] [blame] | 15 | #include <utils_def.h> |
Antonio Nino Diaz | 719bf85 | 2017-02-23 17:22:58 +0000 | [diff] [blame] | 16 | #include <xlat_tables_defs.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 17 | |
| 18 | |
| 19 | /****************************************************************************** |
| 20 | * Definitions common to all ARM standard platforms |
| 21 | *****************************************************************************/ |
| 22 | |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 23 | /* Special value used to verify platform parameters from BL2 to BL31 */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 24 | #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL |
| 25 | |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 26 | #define ARM_SYSTEM_COUNT 1 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 27 | |
| 28 | #define ARM_CACHE_WRITEBACK_SHIFT 6 |
| 29 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 30 | /* |
| 31 | * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The |
| 32 | * power levels have a 1:1 mapping with the MPIDR affinity levels. |
| 33 | */ |
| 34 | #define ARM_PWR_LVL0 MPIDR_AFFLVL0 |
| 35 | #define ARM_PWR_LVL1 MPIDR_AFFLVL1 |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 36 | #define ARM_PWR_LVL2 MPIDR_AFFLVL2 |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 37 | |
| 38 | /* |
| 39 | * Macros for local power states in ARM platforms encoded by State-ID field |
| 40 | * within the power-state parameter. |
| 41 | */ |
| 42 | /* Local power state for power domains in Run state. */ |
| 43 | #define ARM_LOCAL_STATE_RUN 0 |
| 44 | /* Local power state for retention. Valid only for CPU power domains */ |
| 45 | #define ARM_LOCAL_STATE_RET 1 |
| 46 | /* Local power state for OFF/power-down. Valid for CPU and cluster power |
| 47 | domains */ |
| 48 | #define ARM_LOCAL_STATE_OFF 2 |
| 49 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 50 | /* Memory location options for TSP */ |
| 51 | #define ARM_TRUSTED_SRAM_ID 0 |
| 52 | #define ARM_TRUSTED_DRAM_ID 1 |
| 53 | #define ARM_DRAM_ID 2 |
| 54 | |
| 55 | /* The first 4KB of Trusted SRAM are used as shared memory */ |
| 56 | #define ARM_TRUSTED_SRAM_BASE 0x04000000 |
| 57 | #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE |
| 58 | #define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ |
| 59 | |
| 60 | /* The remaining Trusted SRAM is used to load the BL images */ |
| 61 | #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ |
| 62 | ARM_SHARED_RAM_SIZE) |
| 63 | #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ |
| 64 | ARM_SHARED_RAM_SIZE) |
| 65 | |
| 66 | /* |
| 67 | * The top 16MB of DRAM1 is configured as secure access only using the TZC |
| 68 | * - SCP TZC DRAM: If present, DRAM reserved for SCP use |
| 69 | * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use |
| 70 | */ |
David Cunado | 2e36de8 | 2017-01-19 10:26:16 +0000 | [diff] [blame] | 71 | #define ARM_TZC_DRAM1_SIZE ULL(0x01000000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 72 | |
| 73 | #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ |
| 74 | ARM_DRAM1_SIZE - \ |
| 75 | ARM_SCP_TZC_DRAM1_SIZE) |
| 76 | #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE |
| 77 | #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ |
| 78 | ARM_SCP_TZC_DRAM1_SIZE - 1) |
| 79 | |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 80 | /* |
| 81 | * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime |
| 82 | * firmware. This region is meant to be NOLOAD and will not be zero |
| 83 | * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be |
| 84 | * placed here. |
| 85 | */ |
| 86 | #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) |
| 87 | #define ARM_EL3_TZC_DRAM1_SIZE ULL(0x00200000) /* 2 MB */ |
| 88 | #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ |
| 89 | ARM_EL3_TZC_DRAM1_SIZE - 1) |
| 90 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 91 | #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ |
| 92 | ARM_DRAM1_SIZE - \ |
| 93 | ARM_TZC_DRAM1_SIZE) |
| 94 | #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 95 | (ARM_SCP_TZC_DRAM1_SIZE + \ |
| 96 | ARM_EL3_TZC_DRAM1_SIZE)) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 97 | #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ |
| 98 | ARM_AP_TZC_DRAM1_SIZE - 1) |
| 99 | |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 100 | /* Define the Access permissions for Secure peripherals to NS_DRAM */ |
| 101 | #if ARM_CRYPTOCELL_INTEG |
| 102 | /* |
| 103 | * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. |
| 104 | * This is required by CryptoCell to authenticate BL33 which is loaded |
| 105 | * into the Non Secure DDR. |
| 106 | */ |
| 107 | #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD |
| 108 | #else |
| 109 | #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE |
| 110 | #endif |
| 111 | |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 112 | #ifdef SPD_opteed |
| 113 | /* |
Jens Wiklander | ae73b16 | 2017-08-24 15:39:09 +0200 | [diff] [blame] | 114 | * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to |
| 115 | * load/authenticate the trusted os extra image. The first 512KB of |
| 116 | * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading |
| 117 | * for OPTEE is paged image which only include the paging part using |
| 118 | * virtual memory but without "init" data. OPTEE will copy the "init" data |
| 119 | * (from pager image) to the first 512KB of TZC_DRAM, and then copy the |
| 120 | * extra image behind the "init" data. |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 121 | */ |
Jens Wiklander | ae73b16 | 2017-08-24 15:39:09 +0200 | [diff] [blame] | 122 | #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ |
| 123 | ARM_AP_TZC_DRAM1_SIZE - \ |
| 124 | ARM_OPTEE_PAGEABLE_LOAD_SIZE) |
| 125 | #define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 126 | #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ |
| 127 | ARM_OPTEE_PAGEABLE_LOAD_BASE, \ |
| 128 | ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ |
| 129 | MT_MEMORY | MT_RW | MT_SECURE) |
Soby Mathew | 874fc9e | 2017-09-01 13:43:50 +0100 | [diff] [blame] | 130 | |
| 131 | /* |
| 132 | * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging |
| 133 | * support is enabled). |
| 134 | */ |
| 135 | #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ |
| 136 | BL32_BASE, \ |
| 137 | BL32_LIMIT - BL32_BASE, \ |
| 138 | MT_MEMORY | MT_RW | MT_SECURE) |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 139 | #endif /* SPD_opteed */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 140 | |
| 141 | #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE |
| 142 | #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ |
| 143 | ARM_TZC_DRAM1_SIZE) |
| 144 | #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ |
| 145 | ARM_NS_DRAM1_SIZE - 1) |
| 146 | |
David Cunado | 2e36de8 | 2017-01-19 10:26:16 +0000 | [diff] [blame] | 147 | #define ARM_DRAM1_BASE ULL(0x80000000) |
| 148 | #define ARM_DRAM1_SIZE ULL(0x80000000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 149 | #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ |
| 150 | ARM_DRAM1_SIZE - 1) |
| 151 | |
David Cunado | 2e36de8 | 2017-01-19 10:26:16 +0000 | [diff] [blame] | 152 | #define ARM_DRAM2_BASE ULL(0x880000000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 153 | #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE |
| 154 | #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ |
| 155 | ARM_DRAM2_SIZE - 1) |
| 156 | |
| 157 | #define ARM_IRQ_SEC_PHY_TIMER 29 |
| 158 | |
| 159 | #define ARM_IRQ_SEC_SGI_0 8 |
| 160 | #define ARM_IRQ_SEC_SGI_1 9 |
| 161 | #define ARM_IRQ_SEC_SGI_2 10 |
| 162 | #define ARM_IRQ_SEC_SGI_3 11 |
| 163 | #define ARM_IRQ_SEC_SGI_4 12 |
| 164 | #define ARM_IRQ_SEC_SGI_5 13 |
| 165 | #define ARM_IRQ_SEC_SGI_6 14 |
| 166 | #define ARM_IRQ_SEC_SGI_7 15 |
| 167 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 168 | /* |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 169 | * List of secure interrupts are deprecated, but are retained only to support |
| 170 | * legacy configurations. |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 171 | */ |
| 172 | #define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ |
| 173 | ARM_IRQ_SEC_SGI_1, \ |
| 174 | ARM_IRQ_SEC_SGI_2, \ |
| 175 | ARM_IRQ_SEC_SGI_3, \ |
| 176 | ARM_IRQ_SEC_SGI_4, \ |
| 177 | ARM_IRQ_SEC_SGI_5, \ |
| 178 | ARM_IRQ_SEC_SGI_7 |
| 179 | |
| 180 | #define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ |
| 181 | ARM_IRQ_SEC_SGI_6 |
| 182 | |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 183 | /* |
| 184 | * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 |
| 185 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 186 | * as Group 0 interrupts. |
| 187 | */ |
| 188 | #define ARM_G1S_IRQ_PROPS(grp) \ |
| 189 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 190 | GIC_INTR_CFG_LEVEL), \ |
| 191 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 192 | GIC_INTR_CFG_EDGE), \ |
| 193 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 194 | GIC_INTR_CFG_EDGE), \ |
| 195 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 196 | GIC_INTR_CFG_EDGE), \ |
| 197 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 198 | GIC_INTR_CFG_EDGE), \ |
| 199 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 200 | GIC_INTR_CFG_EDGE), \ |
| 201 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 202 | GIC_INTR_CFG_EDGE) |
| 203 | |
| 204 | #define ARM_G0_IRQ_PROPS(grp) \ |
Jeenu Viswambharan | a5acc0a | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 205 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 206 | GIC_INTR_CFG_EDGE), \ |
| 207 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 208 | GIC_INTR_CFG_EDGE) |
| 209 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 210 | #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ |
| 211 | ARM_SHARED_RAM_BASE, \ |
| 212 | ARM_SHARED_RAM_SIZE, \ |
Juan Castillo | 2e86cb1 | 2016-01-13 15:01:09 +0000 | [diff] [blame] | 213 | MT_DEVICE | MT_RW | MT_SECURE) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 214 | |
| 215 | #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ |
| 216 | ARM_NS_DRAM1_BASE, \ |
| 217 | ARM_NS_DRAM1_SIZE, \ |
| 218 | MT_MEMORY | MT_RW | MT_NS) |
| 219 | |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 220 | #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ |
| 221 | ARM_DRAM2_BASE, \ |
| 222 | ARM_DRAM2_SIZE, \ |
| 223 | MT_MEMORY | MT_RW | MT_NS) |
Sandrine Bailleux | b260c3a | 2017-08-30 10:59:22 +0100 | [diff] [blame] | 224 | #ifdef SPD_tspd |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 225 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 226 | #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ |
| 227 | TSP_SEC_MEM_BASE, \ |
| 228 | TSP_SEC_MEM_SIZE, \ |
| 229 | MT_MEMORY | MT_RW | MT_SECURE) |
Sandrine Bailleux | b260c3a | 2017-08-30 10:59:22 +0100 | [diff] [blame] | 230 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 231 | |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 232 | #if ARM_BL31_IN_DRAM |
| 233 | #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ |
| 234 | BL31_BASE, \ |
| 235 | PLAT_ARM_MAX_BL31_SIZE, \ |
| 236 | MT_MEMORY | MT_RW | MT_SECURE) |
| 237 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 238 | |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 239 | #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ |
| 240 | ARM_EL3_TZC_DRAM1_BASE, \ |
| 241 | ARM_EL3_TZC_DRAM1_SIZE, \ |
| 242 | MT_MEMORY | MT_RW | MT_SECURE) |
| 243 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 244 | /* |
| 245 | * The number of regions like RO(code), coherent and data required by |
| 246 | * different BL stages which need to be mapped in the MMU. |
| 247 | */ |
Chris Kay | 2469032 | 2018-05-09 15:14:06 +0100 | [diff] [blame] | 248 | #if ENABLE_SPM && defined(IMAGE_BL31) |
| 249 | # if USE_COHERENT_MEM |
| 250 | # define ARM_BL_REGIONS 5 |
| 251 | # else |
| 252 | # define ARM_BL_REGIONS 4 |
| 253 | # endif |
| 254 | #elif USE_COHERENT_MEM |
| 255 | # define ARM_BL_REGIONS 4 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 256 | #else |
Chris Kay | 2469032 | 2018-05-09 15:14:06 +0100 | [diff] [blame] | 257 | # define ARM_BL_REGIONS 3 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 258 | #endif |
| 259 | |
| 260 | #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ |
| 261 | ARM_BL_REGIONS) |
| 262 | |
| 263 | /* Memory mapped Generic timer interfaces */ |
| 264 | #define ARM_SYS_CNTCTL_BASE 0x2a430000 |
| 265 | #define ARM_SYS_CNTREAD_BASE 0x2a800000 |
| 266 | #define ARM_SYS_TIMCTL_BASE 0x2a810000 |
| 267 | |
| 268 | #define ARM_CONSOLE_BAUDRATE 115200 |
| 269 | |
Juan Castillo | b6132f1 | 2015-10-06 14:01:35 +0100 | [diff] [blame] | 270 | /* Trusted Watchdog constants */ |
| 271 | #define ARM_SP805_TWDG_BASE 0x2a490000 |
| 272 | #define ARM_SP805_TWDG_CLK_HZ 32768 |
| 273 | /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 |
| 274 | * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ |
| 275 | #define ARM_TWDG_TIMEOUT_SEC 128 |
| 276 | #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ |
| 277 | ARM_TWDG_TIMEOUT_SEC) |
| 278 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 279 | /****************************************************************************** |
| 280 | * Required platform porting definitions common to all ARM standard platforms |
| 281 | *****************************************************************************/ |
| 282 | |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 283 | /* |
| 284 | * We need to access DRAM2 from BL2 for PSCI_MEM_PROTECT for |
| 285 | * AArch64 builds |
| 286 | */ |
| 287 | #ifdef AARCH64 |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 288 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) |
| 289 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 290 | #else |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 291 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 292 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 293 | #endif |
| 294 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 295 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 296 | /* |
| 297 | * This macro defines the deepest retention state possible. A higher state |
| 298 | * id will represent an invalid or a power down state. |
| 299 | */ |
| 300 | #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET |
| 301 | |
| 302 | /* |
| 303 | * This macro defines the deepest power down states possible. Any state ID |
| 304 | * higher than this is invalid. |
| 305 | */ |
| 306 | #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF |
| 307 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 308 | /* |
| 309 | * Some data must be aligned on the biggest cache line size in the platform. |
| 310 | * This is known only to the platform as it might have a combination of |
| 311 | * integrated and external caches. |
| 312 | */ |
| 313 | #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) |
| 314 | |
Soby Mathew | 7c6df5b | 2018-01-15 14:43:42 +0000 | [diff] [blame] | 315 | /* |
| 316 | * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base |
| 317 | * and limit. Leave enough space of BL2 meminfo. |
| 318 | */ |
| 319 | #define ARM_TB_FW_CONFIG_BASE ARM_BL_RAM_BASE + sizeof(meminfo_t) |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 320 | #define ARM_TB_FW_CONFIG_LIMIT ARM_BL_RAM_BASE + PAGE_SIZE |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 321 | |
| 322 | /******************************************************************************* |
| 323 | * BL1 specific defines. |
| 324 | * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of |
| 325 | * addresses. |
| 326 | ******************************************************************************/ |
| 327 | #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE |
| 328 | #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ |
| 329 | + PLAT_ARM_TRUSTED_ROM_SIZE) |
| 330 | /* |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 331 | * Put BL1 RW at the top of the Trusted SRAM. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 332 | */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 333 | #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ |
| 334 | ARM_BL_RAM_SIZE - \ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 335 | PLAT_ARM_MAX_BL1_RW_SIZE) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 336 | #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 337 | |
| 338 | /******************************************************************************* |
| 339 | * BL2 specific defines. |
| 340 | ******************************************************************************/ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 341 | #if BL2_AT_EL3 |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 342 | /* Put BL2 towards the middle of the Trusted SRAM */ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 343 | #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 344 | (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) |
Roberto Vargas | 5220780 | 2017-11-17 13:22:18 +0000 | [diff] [blame] | 345 | #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 346 | |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 347 | #else |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 348 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 349 | * Put BL2 just below BL1. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 350 | */ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 351 | #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) |
| 352 | #define BL2_LIMIT BL1_RW_BASE |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 353 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 354 | |
| 355 | /******************************************************************************* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 356 | * BL31 specific defines. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 357 | ******************************************************************************/ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 358 | #if ARM_BL31_IN_DRAM |
| 359 | /* |
| 360 | * Put BL31 at the bottom of TZC secured DRAM |
| 361 | */ |
| 362 | #define BL31_BASE ARM_AP_TZC_DRAM1_BASE |
| 363 | #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
| 364 | PLAT_ARM_MAX_BL31_SIZE) |
Qixiang Xu | a5f7281 | 2017-08-31 11:45:32 +0800 | [diff] [blame] | 365 | #elif (RESET_TO_BL31) |
| 366 | /* |
| 367 | * Put BL31_BASE in the middle of the Trusted SRAM. |
| 368 | */ |
| 369 | #define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \ |
| 370 | (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1)) |
| 371 | #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 372 | #else |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 373 | /* Put BL31 below BL2 in the Trusted SRAM.*/ |
| 374 | #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ |
| 375 | - PLAT_ARM_MAX_BL31_SIZE) |
| 376 | #define BL31_PROGBITS_LIMIT BL2_BASE |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 377 | /* |
| 378 | * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is |
| 379 | * because in the BL2_AT_EL3 configuration, BL2 is always resident. |
| 380 | */ |
| 381 | #if BL2_AT_EL3 |
| 382 | #define BL31_LIMIT BL2_BASE |
| 383 | #else |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 384 | #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 385 | #endif |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 386 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 387 | |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 388 | #if defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 389 | /******************************************************************************* |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 390 | * BL32 specific defines for EL3 runtime in AArch32 mode |
| 391 | ******************************************************************************/ |
| 392 | # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 393 | /* |
| 394 | * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding |
| 395 | * the page reserved for fw_configs) to BL32 |
| 396 | */ |
| 397 | # define BL32_BASE ARM_TB_FW_CONFIG_LIMIT |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 398 | # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 399 | # else |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 400 | /* Put BL32 below BL2 in the Trusted SRAM.*/ |
| 401 | # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ |
| 402 | - PLAT_ARM_MAX_BL32_SIZE) |
| 403 | # define BL32_PROGBITS_LIMIT BL2_BASE |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 404 | # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 405 | # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ |
| 406 | |
| 407 | #else |
| 408 | /******************************************************************************* |
| 409 | * BL32 specific defines for EL3 runtime in AArch64 mode |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 410 | ******************************************************************************/ |
| 411 | /* |
| 412 | * On ARM standard platforms, the TSP can execute from Trusted SRAM, |
| 413 | * Trusted DRAM (if available) or the DRAM region secured by the TrustZone |
| 414 | * controller. |
| 415 | */ |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 416 | # if ENABLE_SPM |
| 417 | # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) |
| 418 | # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) |
| 419 | # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) |
| 420 | # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 421 | ARM_AP_TZC_DRAM1_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 422 | # elif ARM_BL31_IN_DRAM |
| 423 | # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 424 | PLAT_ARM_MAX_BL31_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 425 | # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 426 | PLAT_ARM_MAX_BL31_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 427 | # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 428 | PLAT_ARM_MAX_BL31_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 429 | # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 430 | ARM_AP_TZC_DRAM1_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 431 | # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID |
| 432 | # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE |
| 433 | # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 434 | # define TSP_PROGBITS_LIMIT BL31_BASE |
| 435 | # define BL32_BASE ARM_TB_FW_CONFIG_LIMIT |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 436 | # define BL32_LIMIT BL31_BASE |
| 437 | # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID |
| 438 | # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE |
| 439 | # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE |
| 440 | # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE |
| 441 | # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 442 | + (1 << 21)) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 443 | # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID |
| 444 | # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE |
| 445 | # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE |
| 446 | # define BL32_BASE ARM_AP_TZC_DRAM1_BASE |
| 447 | # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 448 | ARM_AP_TZC_DRAM1_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 449 | # else |
| 450 | # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" |
| 451 | # endif |
| 452 | #endif /* AARCH32 || JUNO_AARCH32_EL3_RUNTIME */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 453 | |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 454 | /* |
| 455 | * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no |
| 456 | * SPD and no SPM, as they are the only ones that can be used as BL32. |
| 457 | */ |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 458 | #if !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 459 | # if defined(SPD_none) && !ENABLE_SPM |
| 460 | # undef BL32_BASE |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 461 | # endif /* defined(SPD_none) && !ENABLE_SPM */ |
| 462 | #endif /* !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) */ |
Antonio Nino Diaz | e4fa370 | 2016-04-05 11:38:49 +0100 | [diff] [blame] | 463 | |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 464 | /******************************************************************************* |
| 465 | * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. |
| 466 | ******************************************************************************/ |
| 467 | #define BL2U_BASE BL2_BASE |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 468 | #define BL2U_LIMIT BL2_LIMIT |
| 469 | |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 470 | #define NS_BL2U_BASE ARM_NS_DRAM1_BASE |
Yatharth Kochar | f11b29a | 2016-02-01 11:04:46 +0000 | [diff] [blame] | 471 | #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000) |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 472 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 473 | /* |
| 474 | * ID of the secure physical generic timer interrupt used by the TSP. |
| 475 | */ |
| 476 | #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER |
| 477 | |
| 478 | |
Vikram Kanigiri | d79214c | 2015-09-09 10:52:13 +0100 | [diff] [blame] | 479 | /* |
| 480 | * One cache line needed for bakery locks on ARM platforms |
| 481 | */ |
| 482 | #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) |
| 483 | |
Jeenu Viswambharan | b183745 | 2017-10-24 11:47:13 +0100 | [diff] [blame] | 484 | /* Priority levels for ARM platforms */ |
Jeenu Viswambharan | a5b5b8d | 2018-02-06 12:21:39 +0000 | [diff] [blame] | 485 | #define PLAT_RAS_PRI 0x10 |
Jeenu Viswambharan | b183745 | 2017-10-24 11:47:13 +0100 | [diff] [blame] | 486 | #define PLAT_SDEI_CRITICAL_PRI 0x60 |
| 487 | #define PLAT_SDEI_NORMAL_PRI 0x70 |
| 488 | |
| 489 | /* ARM platforms use 3 upper bits of secure interrupt priority */ |
| 490 | #define ARM_PRI_BITS 3 |
Vikram Kanigiri | d79214c | 2015-09-09 10:52:13 +0100 | [diff] [blame] | 491 | |
Jeenu Viswambharan | a5acc0a | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 492 | /* SGI used for SDEI signalling */ |
| 493 | #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 |
| 494 | |
| 495 | /* ARM SDEI dynamic private event numbers */ |
| 496 | #define ARM_SDEI_DP_EVENT_0 1000 |
| 497 | #define ARM_SDEI_DP_EVENT_1 1001 |
| 498 | #define ARM_SDEI_DP_EVENT_2 1002 |
| 499 | |
| 500 | /* ARM SDEI dynamic shared event numbers */ |
| 501 | #define ARM_SDEI_DS_EVENT_0 2000 |
| 502 | #define ARM_SDEI_DS_EVENT_1 2001 |
| 503 | #define ARM_SDEI_DS_EVENT_2 2002 |
| 504 | |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 505 | #define ARM_SDEI_PRIVATE_EVENTS \ |
| 506 | SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ |
| 507 | SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 508 | SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 509 | SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) |
| 510 | |
| 511 | #define ARM_SDEI_SHARED_EVENTS \ |
| 512 | SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 513 | SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 514 | SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) |
| 515 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 516 | #endif /* __ARM_DEF_H__ */ |