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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Antonio Nino Diaz719bf852017-02-23 17:22:58 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6#ifndef __V2M_DEF_H__
7#define __V2M_DEF_H__
8
Antonio Nino Diazf09d0032017-04-11 14:04:56 +01009#include <arm_xlat_tables.h>
Dan Handley9df48042015-03-19 18:58:55 +000010
11
12/* V2M motherboard system registers & offsets */
13#define V2M_SYSREGS_BASE 0x1c010000
14#define V2M_SYS_ID 0x0
15#define V2M_SYS_SWITCH 0x4
16#define V2M_SYS_LED 0x8
Juan Castillob6132f12015-10-06 14:01:35 +010017#define V2M_SYS_NVFLAGS 0x38
18#define V2M_SYS_NVFLAGSSET 0x38
19#define V2M_SYS_NVFLAGSCLR 0x3c
Dan Handley9df48042015-03-19 18:58:55 +000020#define V2M_SYS_CFGDATA 0xa0
21#define V2M_SYS_CFGCTRL 0xa4
22#define V2M_SYS_CFGSTATUS 0xa8
23
24#define V2M_CFGCTRL_START (1 << 31)
25#define V2M_CFGCTRL_RW (1 << 30)
26#define V2M_CFGCTRL_FUNC_SHIFT 20
27#define V2M_CFGCTRL_FUNC(fn) (fn << V2M_CFGCTRL_FUNC_SHIFT)
28#define V2M_FUNC_CLK_GEN 0x01
29#define V2M_FUNC_TEMP 0x04
30#define V2M_FUNC_DB_RESET 0x05
31#define V2M_FUNC_SCC_CFG 0x06
32#define V2M_FUNC_SHUTDOWN 0x08
33#define V2M_FUNC_REBOOT 0x09
34
35/*
36 * V2M sysled bit definitions. The values written to this
37 * register are defined in arch.h & runtime_svc.h. Only
38 * used by the primary cpu to diagnose any cold boot issues.
39 *
40 * SYS_LED[0] - Security state (S=0/NS=1)
41 * SYS_LED[2:1] - Exception Level (EL3-EL0)
42 * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
43 *
44 */
45#define V2M_SYS_LED_SS_SHIFT 0x0
46#define V2M_SYS_LED_EL_SHIFT 0x1
47#define V2M_SYS_LED_EC_SHIFT 0x3
48
49#define V2M_SYS_LED_SS_MASK 0x1
50#define V2M_SYS_LED_EL_MASK 0x3
51#define V2M_SYS_LED_EC_MASK 0x1f
52
53/* V2M sysid register bits */
54#define V2M_SYS_ID_REV_SHIFT 28
55#define V2M_SYS_ID_HBI_SHIFT 16
56#define V2M_SYS_ID_BLD_SHIFT 12
57#define V2M_SYS_ID_ARCH_SHIFT 8
58#define V2M_SYS_ID_FPGA_SHIFT 0
59
60#define V2M_SYS_ID_REV_MASK 0xf
61#define V2M_SYS_ID_HBI_MASK 0xfff
62#define V2M_SYS_ID_BLD_MASK 0xf
63#define V2M_SYS_ID_ARCH_MASK 0xf
64#define V2M_SYS_ID_FPGA_MASK 0xff
65
66#define V2M_SYS_ID_BLD_LENGTH 4
67
68
69/* NOR Flash */
70#define V2M_FLASH0_BASE 0x08000000
71#define V2M_FLASH0_SIZE 0x04000000
Roberto Vargasa1c16b62017-08-03 09:16:43 +010072#define V2M_FLASH_BLOCK_SIZE 0x00040000 /* 256 KB */
Dan Handley9df48042015-03-19 18:58:55 +000073
74#define V2M_IOFPGA_BASE 0x1c000000
75#define V2M_IOFPGA_SIZE 0x03000000
76
77/* PL011 UART related constants */
78#define V2M_IOFPGA_UART0_BASE 0x1c090000
79#define V2M_IOFPGA_UART1_BASE 0x1c0a0000
80#define V2M_IOFPGA_UART2_BASE 0x1c0b0000
81#define V2M_IOFPGA_UART3_BASE 0x1c0c0000
82
83#define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000
84#define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000
85#define V2M_IOFPGA_UART2_CLK_IN_HZ 24000000
86#define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000
87
Ryan Harkinf96fc8f2015-03-17 14:54:01 +000088/* SP804 timer related constants */
89#define V2M_SP804_TIMER0_BASE 0x1C110000
90#define V2M_SP804_TIMER1_BASE 0x1C120000
Dan Handley9df48042015-03-19 18:58:55 +000091
Juan Castillofd383b42015-12-01 16:10:15 +000092/* SP810 controller */
93#define V2M_SP810_BASE 0x1c020000
94#define V2M_SP810_CTRL_TIM0_SEL (1 << 15)
95#define V2M_SP810_CTRL_TIM1_SEL (1 << 17)
96#define V2M_SP810_CTRL_TIM2_SEL (1 << 19)
97#define V2M_SP810_CTRL_TIM3_SEL (1 << 21)
98
Sandrine Bailleux889ca032016-06-14 17:01:00 +010099/*
100 * The flash can be mapped either as read-only or read-write.
101 *
102 * If it is read-write then it should also be mapped as device memory because
103 * NOR flash programming involves sending a fixed, ordered sequence of commands.
104 *
105 * If it is read-only then it should also be mapped as:
106 * - Normal memory, because reading from NOR flash is transparent, it is like
107 * reading from RAM.
108 * - Non-executable by default. If some parts of the flash need to be executable
109 * then platform code is responsible for re-mapping the appropriate portion
110 * of it as executable.
111 */
Juan Castillob6132f12015-10-06 14:01:35 +0100112#define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\
113 V2M_FLASH0_SIZE, \
114 MT_DEVICE | MT_RW | MT_SECURE)
115
116#define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
Dan Handley9df48042015-03-19 18:58:55 +0000117 V2M_FLASH0_SIZE, \
Sandrine Bailleux889ca032016-06-14 17:01:00 +0100118 MT_RO_DATA | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +0000119
120#define V2M_MAP_IOFPGA MAP_REGION_FLAT(V2M_IOFPGA_BASE,\
121 V2M_IOFPGA_SIZE, \
122 MT_DEVICE | MT_RW | MT_SECURE)
123
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000124/* Region equivalent to V2M_MAP_IOFPGA suitable for mapping at EL0 */
125#define V2M_MAP_IOFPGA_EL0 MAP_REGION_FLAT( \
126 V2M_IOFPGA_BASE, \
127 V2M_IOFPGA_SIZE, \
128 MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
Dan Handley9df48042015-03-19 18:58:55 +0000129
130
131#endif /* __V2M_DEF_H__ */