Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 1 | /* |
Govindraj Raja | eee28e7 | 2023-08-01 15:52:40 -0500 | [diff] [blame] | 2 | * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 6 | |
| 7 | #include <lib/extensions/ras_arch.h> |
| 8 | #include <lib/utils_def.h> |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 9 | |
| 10 | /* |
| 11 | * Probe for error in memory-mapped registers containing error records |
| 12 | * implemented Standard Error Record format. Upon detecting an error, set probe |
| 13 | * data to the index of the record in error, and return 1; otherwise, return 0. |
| 14 | */ |
| 15 | int ser_probe_memmap(uintptr_t base, unsigned int size_num_k, int *probe_data) |
| 16 | { |
Jeenu Viswambharan | 31ac01e | 2018-08-02 10:14:12 +0100 | [diff] [blame] | 17 | unsigned int num_records, num_group_regs, i; |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 18 | uint64_t gsr; |
| 19 | |
Jeenu Viswambharan | 31ac01e | 2018-08-02 10:14:12 +0100 | [diff] [blame] | 20 | assert(base != 0UL); |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 21 | |
| 22 | /* Only 4K supported for now */ |
| 23 | assert(size_num_k == STD_ERR_NODE_SIZE_NUM_K); |
| 24 | |
Jeenu Viswambharan | 31ac01e | 2018-08-02 10:14:12 +0100 | [diff] [blame] | 25 | num_records = (unsigned int) |
| 26 | (mmio_read_32(ERR_DEVID(base, size_num_k)) & ERR_DEVID_MASK); |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 27 | |
| 28 | /* A group register shows error status for 2^6 error records */ |
Jeenu Viswambharan | 31ac01e | 2018-08-02 10:14:12 +0100 | [diff] [blame] | 29 | num_group_regs = (num_records >> 6U) + 1U; |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 30 | |
| 31 | /* Iterate through group registers to find a record in error */ |
| 32 | for (i = 0; i < num_group_regs; i++) { |
| 33 | gsr = mmio_read_64(ERR_GSR(base, size_num_k, i)); |
Jeenu Viswambharan | 31ac01e | 2018-08-02 10:14:12 +0100 | [diff] [blame] | 34 | if (gsr == 0ULL) |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 35 | continue; |
| 36 | |
| 37 | /* Return the index of the record in error */ |
| 38 | if (probe_data != NULL) |
Jeenu Viswambharan | 31ac01e | 2018-08-02 10:14:12 +0100 | [diff] [blame] | 39 | *probe_data = (((int) (i << 6U)) + __builtin_ctzll(gsr)); |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 40 | |
| 41 | return 1; |
| 42 | } |
| 43 | |
| 44 | return 0; |
| 45 | } |
| 46 | |
| 47 | /* |
| 48 | * Probe for error in System Registers where error records are implemented in |
| 49 | * Standard Error Record format. Upon detecting an error, set probe data to the |
| 50 | * index of the record in error, and return 1; otherwise, return 0. |
| 51 | */ |
| 52 | int ser_probe_sysreg(unsigned int idx_start, unsigned int num_idx, int *probe_data) |
| 53 | { |
Jeenu Viswambharan | 31ac01e | 2018-08-02 10:14:12 +0100 | [diff] [blame] | 54 | unsigned int i; |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 55 | uint64_t status; |
Jeenu Viswambharan | 31ac01e | 2018-08-02 10:14:12 +0100 | [diff] [blame] | 56 | unsigned int max_idx __unused = |
| 57 | ((unsigned int) read_erridr_el1()) & ERRIDR_MASK; |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 58 | |
| 59 | assert(idx_start < max_idx); |
Jeenu Viswambharan | 067a357 | 2018-09-07 16:30:58 +0100 | [diff] [blame] | 60 | assert(check_u32_overflow(idx_start, num_idx) == 0); |
Jeenu Viswambharan | 31ac01e | 2018-08-02 10:14:12 +0100 | [diff] [blame] | 61 | assert((idx_start + num_idx - 1U) < max_idx); |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 62 | |
| 63 | for (i = 0; i < num_idx; i++) { |
| 64 | /* Select the error record */ |
| 65 | ser_sys_select_record(idx_start + i); |
| 66 | |
| 67 | /* Retrieve status register from the error record */ |
| 68 | status = read_erxstatus_el1(); |
| 69 | |
| 70 | /* Check for valid field in status */ |
Jeenu Viswambharan | 31ac01e | 2018-08-02 10:14:12 +0100 | [diff] [blame] | 71 | if (ERR_STATUS_GET_FIELD(status, V) != 0U) { |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 72 | if (probe_data != NULL) |
Jeenu Viswambharan | 31ac01e | 2018-08-02 10:14:12 +0100 | [diff] [blame] | 73 | *probe_data = (int) i; |
Jeenu Viswambharan | 19f6cf2 | 2017-12-07 08:43:05 +0000 | [diff] [blame] | 74 | return 1; |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | return 0; |
| 79 | } |