blob: 632af7b409f223d529d7094af89b41adbb9e8d78 [file] [log] [blame]
Deepak Pandey9cbacf62018-08-08 10:32:51 +05301/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Antonio Nino Diaz1b0c6f12019-01-23 21:08:43 +00009#include <drivers/arm/css/css_mhu_doorbell.h>
Antonio Nino Diazc30db5b2019-01-23 20:37:32 +000010#include <drivers/arm/css/scmi.h>
Manoj Kumar69bebd82019-06-21 17:07:13 +010011#include <drivers/arm/css/sds.h>
12#include <common/debug.h>
13#include <lib/mmio.h>
14#include <lib/utils.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000015#include <plat/arm/common/plat_arm.h>
16
Manoj Kumar69bebd82019-06-21 17:07:13 +010017#include "n1sdp_def.h"
18
19/*
20 * Memory information structure stored in SDS.
21 * This structure holds the total DDR memory size which will be
22 * used when zeroing out the entire DDR memory before enabling
23 * the ECC capability in DMCs.
24 */
25struct n1sdp_mem_info {
26 uint32_t ddr_size_gb;
27};
28
29/*
30 * BL33 image information structure stored in SDS.
31 * This structure holds the source & destination addresses and
32 * the size of the BL33 image which will be loaded by BL31.
33 */
34struct n1sdp_bl33_info {
35 uint32_t bl33_src_addr;
36 uint32_t bl33_dst_addr;
37 uint32_t bl33_size;
38};
39
Deepak Pandey9cbacf62018-08-08 10:32:51 +053040static scmi_channel_plat_info_t n1sdp_scmi_plat_info = {
41 .scmi_mbx_mem = N1SDP_SCMI_PAYLOAD_BASE,
42 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
43 .db_preserve_mask = 0xfffffffe,
44 .db_modify_mask = 0x1,
45 .ring_doorbell = &mhu_ring_doorbell,
46};
47
48scmi_channel_plat_info_t *plat_css_get_scmi_info()
49{
50 return &n1sdp_scmi_plat_info;
51}
Chandni Cherukurie4bf6a02018-11-14 13:43:59 +053052
53const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
54{
55 return css_scmi_override_pm_ops(ops);
56}
Manoj Kumar69bebd82019-06-21 17:07:13 +010057
58/*
59 * N1SDP platform supports RDIMMs with ECC capability. To use the ECC
60 * capability, the entire DDR memory space has to be zeroed out before
61 * enabling the ECC bits in DMC620. Zeroing out several gigabytes of
62 * memory from SCP is quite time consuming so the following function
63 * is added to zero out the DDR memory from application processor which is
64 * much faster compared to SCP. BL33 binary cannot be copied to DDR memory
65 * before enabling ECC so copy_bl33 function is added to copy BL33 binary
66 * from IOFPGA-DDR3 memory to main DDR4 memory.
67 */
68
69void dmc_ecc_setup(uint32_t ddr_size_gb)
70{
71 uint64_t dram2_size;
72
73 dram2_size = (ddr_size_gb * 1024UL * 1024UL * 1024UL) -
74 ARM_DRAM1_SIZE;
75
76 INFO("Zeroing DDR memories\n");
77 zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
78 flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
79 zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size);
80 flush_dcache_range(ARM_DRAM2_BASE, dram2_size);
81
82 INFO("Enabling ECC on DMCs\n");
Manoj Kumar75e4ccb2019-07-22 16:10:12 +010083 /* Set DMCs to CONFIG state before writing ERR0CTLR0 register */
84 mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
85 mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
86
87 /* Enable ECC in DMCs */
Manoj Kumar69bebd82019-06-21 17:07:13 +010088 mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
89 mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
Manoj Kumar75e4ccb2019-07-22 16:10:12 +010090
91 /* Set DMCs to READY state */
92 mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
93 mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
Manoj Kumar69bebd82019-06-21 17:07:13 +010094}
95
96void copy_bl33(uint32_t src, uint32_t dst, uint32_t size)
97{
98 uint32_t i;
99
100 INFO("Copying BL33 to DDR memory\n");
101 for (i = 0; i < size; i = i + 8)
102 mmio_write_64((dst + i), mmio_read_64(src + i));
103
104 for (i = 0; i < size; i = i + 8) {
105 if (mmio_read_64(src + i) != mmio_read_64(dst + i)) {
106 ERROR("Copy failed!\n");
107 panic();
108 }
109 }
110}
111
112void bl31_platform_setup(void)
113{
114 int ret;
115 struct n1sdp_mem_info mem_info;
116 struct n1sdp_bl33_info bl33_info;
117
118 arm_bl31_platform_setup();
119
120 ret = sds_init();
121 if (ret != SDS_OK) {
122 ERROR("SDS initialization failed\n");
123 panic();
124 }
125
126 ret = sds_struct_read(N1SDP_SDS_MEM_INFO_STRUCT_ID,
127 N1SDP_SDS_MEM_INFO_OFFSET,
128 &mem_info,
129 N1SDP_SDS_MEM_INFO_SIZE,
130 SDS_ACCESS_MODE_NON_CACHED);
131 if (ret != SDS_OK) {
132 ERROR("Error getting memory info from SDS\n");
133 panic();
134 }
135 dmc_ecc_setup(mem_info.ddr_size_gb);
136
137 ret = sds_struct_read(N1SDP_SDS_BL33_INFO_STRUCT_ID,
138 N1SDP_SDS_BL33_INFO_OFFSET,
139 &bl33_info,
140 N1SDP_SDS_BL33_INFO_SIZE,
141 SDS_ACCESS_MODE_NON_CACHED);
142 if (ret != SDS_OK) {
143 ERROR("Error getting BL33 info from SDS\n");
144 panic();
145 }
146 copy_bl33(bl33_info.bl33_src_addr,
147 bl33_info.bl33_dst_addr,
148 bl33_info.bl33_size);
149 /*
150 * Pass DDR memory size info to BL33. This method is followed as
151 * currently there is no BL1/BL2 involved in boot flow of N1SDP.
152 * When TBBR is implemented for N1SDP, this method should be removed
153 * and DDR memory size shoule be passed to BL33 using NT_FW_CONFIG
154 * passing mechanism.
155 */
156 mmio_write_32(N1SDP_DDR_MEM_INFO_BASE, mem_info.ddr_size_gb);
157}