Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <assert.h> |
| 10 | #include <common/bl_common.h> |
| 11 | #include <context.h> |
| 12 | #include <lib/el3_runtime/context_mgmt.h> |
| 13 | #include <common/debug.h> |
| 14 | #include <denver.h> |
| 15 | #include <mce.h> |
| 16 | #include <mce_private.h> |
| 17 | #include <mmio.h> |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 18 | #include <platform_def.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 19 | #include <string.h> |
| 20 | #include <errno.h> |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 21 | #include <t194_nvg.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 22 | #include <tegra_def.h> |
| 23 | #include <tegra_platform.h> |
| 24 | |
| 25 | /******************************************************************************* |
| 26 | * Common handler for all MCE commands |
| 27 | ******************************************************************************/ |
Anthony Zhou | 5e890b3 | 2017-04-28 13:52:58 +0800 | [diff] [blame] | 28 | int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 29 | uint64_t arg2) |
| 30 | { |
| 31 | uint64_t ret64 = 0, arg3, arg4, arg5; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 32 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 33 | cpu_context_t *ctx = cm_get_context(NON_SECURE); |
| 34 | gp_regs_t *gp_regs = get_gpregs_ctx(ctx); |
| 35 | |
| 36 | assert(ctx); |
| 37 | assert(gp_regs); |
| 38 | |
| 39 | switch (cmd) { |
| 40 | case MCE_CMD_ENTER_CSTATE: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 41 | ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1); |
| 42 | if (ret < 0) { |
| 43 | ERROR("%s: enter_cstate failed(%d)\n", __func__, ret); |
| 44 | } |
| 45 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 46 | break; |
| 47 | |
| 48 | case MCE_CMD_UPDATE_CSTATE_INFO: |
| 49 | /* |
| 50 | * get the parameters required for the update cstate info |
| 51 | * command |
| 52 | */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 53 | arg3 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4)); |
| 54 | arg4 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5)); |
| 55 | arg5 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6)); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 56 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 57 | /* arg0 cluster |
| 58 | * arg1 ccplex |
| 59 | * arg2 system |
| 60 | * arg3 sys_state_force => T19x not support |
| 61 | * arg4 wake_mask |
| 62 | * arg5 update_wake_mask |
| 63 | */ |
| 64 | nvg_update_cstate_info((uint32_t)arg0, (uint32_t)arg1, |
| 65 | (uint32_t)arg2, (uint32_t)arg4, (uint8_t)arg5); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 66 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 67 | write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4), (arg3)); |
| 68 | write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5), (arg4)); |
| 69 | write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6), (arg5)); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 70 | |
| 71 | break; |
| 72 | |
| 73 | case MCE_CMD_UPDATE_CROSSOVER_TIME: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 74 | ret = nvg_update_crossover_time((uint32_t)arg0, (uint32_t)arg1); |
| 75 | if (ret < 0) { |
| 76 | ERROR("%s: update_crossover_time failed(%d)\n", |
| 77 | __func__, ret); |
| 78 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 79 | |
| 80 | break; |
| 81 | |
| 82 | case MCE_CMD_READ_CSTATE_STATS: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 83 | ret64 = nvg_get_cstate_stat_query_value(); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 84 | |
| 85 | /* update context to return cstate stats value */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 86 | write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64)); |
| 87 | write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64)); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 88 | |
| 89 | break; |
| 90 | |
| 91 | case MCE_CMD_WRITE_CSTATE_STATS: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 92 | ret = nvg_set_cstate_stat_query_value(arg0); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 93 | |
| 94 | break; |
| 95 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 96 | case MCE_CMD_IS_SC7_ALLOWED: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 97 | ret = nvg_is_sc7_allowed(); |
| 98 | if (ret < 0) { |
| 99 | ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret); |
| 100 | break; |
| 101 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 102 | |
| 103 | /* update context to return SC7 status value */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 104 | write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), ((uint64_t)ret)); |
| 105 | write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X3), ((uint64_t)ret)); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 106 | |
| 107 | break; |
| 108 | |
| 109 | case MCE_CMD_ONLINE_CORE: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 110 | ret = nvg_online_core((uint32_t)arg0); |
| 111 | if (ret < 0) { |
| 112 | ERROR("%s: online_core failed(%d)\n", __func__, ret); |
| 113 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 114 | |
| 115 | break; |
| 116 | |
| 117 | case MCE_CMD_CC3_CTRL: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 118 | ret = nvg_cc3_ctrl((uint32_t)arg0, (uint8_t)arg2); |
| 119 | if (ret < 0) { |
| 120 | ERROR("%s: cc3_ctrl failed(%d)\n", __func__, ret); |
| 121 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 122 | |
| 123 | break; |
| 124 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 125 | case MCE_CMD_READ_VERSIONS: |
| 126 | /* get the MCE firmware version */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 127 | ret64 = nvg_get_version(); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 128 | |
| 129 | /* |
| 130 | * version = minor(63:32) | major(31:0). Update context |
| 131 | * to return major and minor version number. |
| 132 | */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 133 | write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64 & (uint64_t)0xFFFF)); |
| 134 | write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64 >> 32)); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 135 | |
| 136 | break; |
| 137 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 138 | case MCE_CMD_ROC_FLUSH_CACHE_TRBITS: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 139 | ret = nvg_roc_clean_cache_trbits(); |
| 140 | if (ret < 0) { |
| 141 | ERROR("%s: flush cache_trbits failed(%d)\n", __func__, |
| 142 | ret); |
| 143 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 144 | |
| 145 | break; |
| 146 | |
| 147 | case MCE_CMD_ROC_FLUSH_CACHE: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 148 | ret = nvg_roc_flush_cache(); |
| 149 | if (ret < 0) { |
| 150 | ERROR("%s: flush cache failed(%d)\n", __func__, ret); |
| 151 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 152 | |
| 153 | break; |
| 154 | |
| 155 | case MCE_CMD_ROC_CLEAN_CACHE: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 156 | ret = nvg_roc_clean_cache(); |
| 157 | if (ret < 0) { |
| 158 | ERROR("%s: clean cache failed(%d)\n", __func__, ret); |
| 159 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 160 | |
| 161 | break; |
| 162 | |
| 163 | default: |
Anthony Zhou | 5e890b3 | 2017-04-28 13:52:58 +0800 | [diff] [blame] | 164 | ERROR("unknown MCE command (%llu)\n", cmd); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 165 | ret = EINVAL; |
| 166 | break; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | return ret; |
| 170 | } |
| 171 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 172 | /******************************************************************************* |
| 173 | * Handler to update carveout values for Video Memory Carveout region |
| 174 | ******************************************************************************/ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 175 | int32_t mce_update_gsc_videomem(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 176 | { |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 177 | return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_VPR_IDX); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | /******************************************************************************* |
| 181 | * Handler to update carveout values for TZDRAM aperture |
| 182 | ******************************************************************************/ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 183 | int32_t mce_update_gsc_tzdram(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 184 | { |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 185 | return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZ_DRAM_IDX); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 186 | } |
| 187 | |
| 188 | /******************************************************************************* |
| 189 | * Handler to update carveout values for TZ SysRAM aperture |
| 190 | ******************************************************************************/ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 191 | int32_t mce_update_gsc_tzram(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 192 | { |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 193 | return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZRAM); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 194 | } |
| 195 | |
| 196 | /******************************************************************************* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 197 | * Handler to issue the UPDATE_CSTATE_INFO request |
| 198 | ******************************************************************************/ |
Anthony Zhou | 5e890b3 | 2017-04-28 13:52:58 +0800 | [diff] [blame] | 199 | void mce_update_cstate_info(const mce_cstate_info_t *cstate) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 200 | { |
| 201 | /* issue the UPDATE_CSTATE_INFO request */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 202 | nvg_update_cstate_info(cstate->cluster, cstate->ccplex, cstate->system, |
| 203 | cstate->wake_mask, cstate->update_wake_mask); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 204 | } |
| 205 | |
| 206 | /******************************************************************************* |
| 207 | * Handler to read the MCE firmware version and check if it is compatible |
| 208 | * with interface header the BL3-1 was compiled against |
| 209 | ******************************************************************************/ |
| 210 | void mce_verify_firmware_version(void) |
| 211 | { |
| 212 | uint64_t version; |
| 213 | uint32_t major, minor; |
| 214 | |
| 215 | /* |
| 216 | * MCE firmware is not running on simulation platforms. |
| 217 | */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 218 | if ((tegra_platform_is_linsim() == 1U) || |
Rohit Khanna | f2cb2d9 | 2017-03-03 11:33:32 -0800 | [diff] [blame] | 219 | (tegra_platform_is_virt_dev_kit() == 1U) || |
| 220 | (tegra_platform_is_qt() == 1U)) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 221 | return; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 222 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 223 | |
| 224 | /* |
| 225 | * Read the MCE firmware version and extract the major and minor |
| 226 | * version fields |
| 227 | */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 228 | version = nvg_get_version(); |
| 229 | minor = (uint32_t)version; |
| 230 | major = (uint32_t)(version >> 32); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 231 | |
| 232 | INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor, |
| 233 | 0, 0); |
| 234 | |
| 235 | /* |
| 236 | * Verify that the MCE firmware version and the interface header |
| 237 | * match |
| 238 | */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 239 | if (major != (uint32_t)TEGRA_NVG_VERSION_MAJOR) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 240 | ERROR("MCE major version mismatch\n"); |
| 241 | panic(); |
| 242 | } |
| 243 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 244 | if (minor < (uint32_t)TEGRA_NVG_VERSION_MINOR) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 245 | ERROR("MCE minor version mismatch\n"); |
| 246 | panic(); |
| 247 | } |
| 248 | } |