| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | |
| 10 | .globl nvg_set_request_data |
| 11 | .globl nvg_set_request |
| 12 | .globl nvg_get_result |
| Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame^] | 13 | .globl nvg_cache_clean |
| 14 | .globl nvg_cache_clean_inval |
| 15 | .globl nvg_cache_inval_all |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 16 | |
| 17 | /* void nvg_set_request_data(uint64_t req, uint64_t data) */ |
| 18 | func nvg_set_request_data |
| 19 | msr s3_0_c15_c1_2, x0 |
| 20 | msr s3_0_c15_c1_3, x1 |
| 21 | ret |
| 22 | endfunc nvg_set_request_data |
| 23 | |
| 24 | /* void nvg_set_request(uint64_t req) */ |
| 25 | func nvg_set_request |
| 26 | msr s3_0_c15_c1_2, x0 |
| 27 | ret |
| 28 | endfunc nvg_set_request |
| 29 | |
| 30 | /* uint64_t nvg_get_result(void) */ |
| 31 | func nvg_get_result |
| 32 | mrs x0, s3_0_c15_c1_3 |
| 33 | ret |
| 34 | endfunc nvg_get_result |
| Steven Kao | 238d6d2 | 2017-08-16 20:12:00 +0800 | [diff] [blame^] | 35 | |
| 36 | /* uint64_t nvg_cache_clean(void) */ |
| 37 | func nvg_cache_clean |
| 38 | mrs x0, s3_0_c15_c3_5 |
| 39 | ret |
| 40 | endfunc nvg_cache_clean |
| 41 | |
| 42 | /* uint64_t nvg_cache_clean_inval(void) */ |
| 43 | func nvg_cache_clean_inval |
| 44 | mrs x0, s3_0_c15_c3_6 |
| 45 | ret |
| 46 | endfunc nvg_cache_clean_inval |
| 47 | |
| 48 | /* uint64_t nvg_cache_inval_all(void) */ |
| 49 | func nvg_cache_inval_all |
| 50 | mrs x0, s3_0_c15_c3_7 |
| 51 | ret |
| 52 | endfunc nvg_cache_inval_all |