Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022, ARM Limited. All rights reserved. |
Varun Wadekar | 0a46eb1 | 2023-04-13 21:06:18 +0100 | [diff] [blame] | 3 | * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | * |
| 7 | * Dispatch synchronous system register traps from lower ELs. |
| 8 | */ |
| 9 | |
| 10 | #include <bl31/sync_handle.h> |
| 11 | #include <context.h> |
| 12 | |
| 13 | int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx) |
| 14 | { |
Varun Wadekar | 0a46eb1 | 2023-04-13 21:06:18 +0100 | [diff] [blame] | 15 | uint64_t __unused opcode = esr_el3 & ISS_SYSREG_OPCODE_MASK; |
| 16 | |
Andre Przywara | bdc76f1 | 2022-11-21 17:07:25 +0000 | [diff] [blame] | 17 | #if ENABLE_FEAT_RNG_TRAP |
Varun Wadekar | 0a46eb1 | 2023-04-13 21:06:18 +0100 | [diff] [blame] | 18 | if ((opcode == ISS_SYSREG_OPCODE_RNDR) || (opcode == ISS_SYSREG_OPCODE_RNDRRS)) { |
Andre Przywara | bdc76f1 | 2022-11-21 17:07:25 +0000 | [diff] [blame] | 19 | return plat_handle_rng_trap(esr_el3, ctx); |
Varun Wadekar | 0a46eb1 | 2023-04-13 21:06:18 +0100 | [diff] [blame] | 20 | } |
Andre Przywara | bdc76f1 | 2022-11-21 17:07:25 +0000 | [diff] [blame] | 21 | #endif |
Varun Wadekar | 0a46eb1 | 2023-04-13 21:06:18 +0100 | [diff] [blame] | 22 | |
| 23 | #if IMPDEF_SYSREG_TRAP |
| 24 | if ((opcode & ISS_SYSREG_OPCODE_IMPDEF) == ISS_SYSREG_OPCODE_IMPDEF) { |
| 25 | return plat_handle_impdef_trap(esr_el3, ctx); |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 26 | } |
Varun Wadekar | 0a46eb1 | 2023-04-13 21:06:18 +0100 | [diff] [blame] | 27 | #endif |
| 28 | |
| 29 | return TRAP_RET_UNHANDLED; |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 30 | } |