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Soby Mathewd29f67b2016-05-05 12:31:57 +01001/*
Jeenu Viswambharan54ec86a2017-01-19 14:23:36 +00002 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathewd29f67b2016-05-05 12:31:57 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#ifndef __ASM_MACROS_S__
31#define __ASM_MACROS_S__
32
33#include <arch.h>
34#include <asm_macros_common.S>
Jeenu Viswambharan54ec86a2017-01-19 14:23:36 +000035#include <spinlock.h>
Soby Mathewd29f67b2016-05-05 12:31:57 +010036
37#define WORD_SIZE 4
38
39 /*
40 * Co processor register accessors
41 */
42 .macro ldcopr reg, coproc, opc1, CRn, CRm, opc2
43 mrc \coproc, \opc1, \reg, \CRn, \CRm, \opc2
44 .endm
45
46 .macro ldcopr16 reg1, reg2, coproc, opc1, CRm
47 mrrc \coproc, \opc1, \reg1, \reg2, \CRm
48 .endm
49
50 .macro stcopr reg, coproc, opc1, CRn, CRm, opc2
51 mcr \coproc, \opc1, \reg, \CRn, \CRm, \opc2
52 .endm
53
54 .macro stcopr16 reg1, reg2, coproc, opc1, CRm
55 mcrr \coproc, \opc1, \reg1, \reg2, \CRm
56 .endm
57
58 /* Cache line size helpers */
59 .macro dcache_line_size reg, tmp
60 ldcopr \tmp, CTR
61 ubfx \tmp, \tmp, #CTR_DMINLINE_SHIFT, #CTR_DMINLINE_WIDTH
62 mov \reg, #WORD_SIZE
63 lsl \reg, \reg, \tmp
64 .endm
65
66 .macro icache_line_size reg, tmp
67 ldcopr \tmp, CTR
68 and \tmp, \tmp, #CTR_IMINLINE_MASK
69 mov \reg, #WORD_SIZE
70 lsl \reg, \reg, \tmp
71 .endm
72
73 /*
Yatharth Kocharf528faf2016-06-28 16:58:26 +010074 * Declare the exception vector table, enforcing it is aligned on a
75 * 32 byte boundary.
76 */
77 .macro vector_base label
78 .section .vectors, "ax"
79 .align 5
80 \label:
81 .endm
82
83 /*
Soby Mathewd29f67b2016-05-05 12:31:57 +010084 * This macro calculates the base address of the current CPU's multi
85 * processor(MP) stack using the plat_my_core_pos() index, the name of
86 * the stack storage and the size of each stack.
87 * Out: r0 = physical address of stack base
88 * Clobber: r14, r1, r2
89 */
90 .macro get_my_mp_stack _name, _size
91 bl plat_my_core_pos
92 ldr r2, =(\_name + \_size)
93 mov r1, #\_size
94 mla r0, r0, r1, r2
95 .endm
96
97 /*
98 * This macro calculates the base address of a uniprocessor(UP) stack
99 * using the name of the stack storage and the size of the stack
100 * Out: r0 = physical address of stack base
101 */
102 .macro get_up_stack _name, _size
103 ldr r0, =(\_name + \_size)
104 .endm
105
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000106 /*
107 * Macro to mark instances where we're jumping to a function and don't
108 * expect a return. To provide the function being jumped to with
109 * additional information, we use 'bl' instruction to jump rather than
110 * 'b'.
111 *
112 * Debuggers infer the location of a call from where LR points to, which
113 * is usually the instruction after 'bl'. If this macro expansion
114 * happens to be the last location in a function, that'll cause the LR
115 * to point a location beyond the function, thereby misleading debugger
116 * back trace. We therefore insert a 'nop' after the function call for
117 * debug builds, unless 'skip_nop' parameter is non-zero.
118 */
119 .macro no_ret _func:req, skip_nop=0
120 bl \_func
121#if DEBUG
122 .ifeq \skip_nop
123 nop
124 .endif
125#endif
126 .endm
127
Jeenu Viswambharan54ec86a2017-01-19 14:23:36 +0000128 /*
129 * Reserve space for a spin lock in assembly file.
130 */
131 .macro define_asm_spinlock _name:req
132 .align SPINLOCK_ASM_ALIGN
133 \_name:
134 .space SPINLOCK_ASM_SIZE
135 .endm
136
Soby Mathewd29f67b2016-05-05 12:31:57 +0100137#endif /* __ASM_MACROS_S__ */