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Caesar Wangd90f43e2016-10-11 09:36:00 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Caesar Wangd90f43e2016-10-11 09:36:00 +08005 */
6#ifndef __ROCKCHIP_PLAT_LD_S__
7#define __ROCKCHIP_PLAT_LD_S__
8
9MEMORY {
10 SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE
Lin Huang30e43392017-05-04 16:02:45 +080011 PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
Caesar Wangd90f43e2016-10-11 09:36:00 +080012}
13
14SECTIONS
15{
16 . = SRAM_BASE;
17 ASSERT(. == ALIGN(4096),
18 "SRAM_BASE address is not aligned on a page boundary.")
19
20 /*
21 * The SRAM space allocation for RK3399
22 * ----------------
Caesar Wangb4003742016-10-12 08:10:12 +080023 * | m0 code bin
24 * ----------------
Caesar Wangd90f43e2016-10-11 09:36:00 +080025 * | sram text
26 * ----------------
27 * | sram data
28 * ----------------
29 */
Caesar Wangb4003742016-10-12 08:10:12 +080030 .incbin_sram : ALIGN(4096) {
31 __sram_incbin_start = .;
32 *(.sram.incbin)
Lin Huang88dd1232017-05-16 16:40:46 +080033 __sram_incbin_real_end = .;
Caesar Wangb4003742016-10-12 08:10:12 +080034 . = ALIGN(4096);
35 __sram_incbin_end = .;
36 } >SRAM
Lin Huang88dd1232017-05-16 16:40:46 +080037 ASSERT((__sram_incbin_real_end - __sram_incbin_start) <=
38 SRAM_BIN_LIMIT, ".incbin_sram has exceeded its limit")
Caesar Wangb4003742016-10-12 08:10:12 +080039
Caesar Wangd90f43e2016-10-11 09:36:00 +080040 .text_sram : ALIGN(4096) {
41 __bl31_sram_text_start = .;
42 *(.sram.text)
43 *(.sram.rodata)
Lin Huang88dd1232017-05-16 16:40:46 +080044 __bl31_sram_text_real_end = .;
Caesar Wangd90f43e2016-10-11 09:36:00 +080045 . = ALIGN(4096);
46 __bl31_sram_text_end = .;
47 } >SRAM
Lin Huang88dd1232017-05-16 16:40:46 +080048 ASSERT((__bl31_sram_text_real_end - __bl31_sram_text_start) <=
49 SRAM_TEXT_LIMIT, ".text_sram has exceeded its limit")
Caesar Wangd90f43e2016-10-11 09:36:00 +080050
51 .data_sram : ALIGN(4096) {
52 __bl31_sram_data_start = .;
53 *(.sram.data)
Lin Huang88dd1232017-05-16 16:40:46 +080054 __bl31_sram_data_real_end = .;
Caesar Wangd90f43e2016-10-11 09:36:00 +080055 . = ALIGN(4096);
56 __bl31_sram_data_end = .;
57 } >SRAM
Lin Huang88dd1232017-05-16 16:40:46 +080058 ASSERT((__bl31_sram_data_real_end - __bl31_sram_data_start) <=
59 SRAM_DATA_LIMIT, ".data_sram has exceeded its limit")
Lin Huang30e43392017-05-04 16:02:45 +080060
61 .stack_sram : ALIGN(4096) {
62 __bl31_sram_stack_start = .;
63 . += 4096;
64 __bl31_sram_stack_end = .;
65 } >SRAM
66
67 . = PMUSRAM_BASE;
68
69 /*
70 * pmu_cpuson_entrypoint request address
71 * align 64K when resume, so put it in the
72 * start of pmusram
73 */
74 .pmusram : {
75 ASSERT(. == ALIGN(64 * 1024),
76 ".pmusram.entry request 64K aligned.");
77 *(.pmusram.entry)
78 __bl31_pmusram_text_start = .;
79 *(.pmusram.text)
80 *(.pmusram.rodata)
81 __bl31_pmusram_text_end = .;
82 __bl31_pmusram_data_start = .;
83 *(.pmusram.data)
84 __bl31_pmusram_data_end = .;
85
86 } >PMUSRAM
Caesar Wangd90f43e2016-10-11 09:36:00 +080087}
88
89#endif /* __ROCKCHIP_PLAT_LD_S__ */