Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 1eb64a1 | 2018-10-17 15:29:34 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
| 8 | #include <assert_macros.S> |
| 9 | #include <cpu_macros.S> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 10 | #include <cortex_a53.h> |
Isla Mitchell | e363146 | 2017-07-14 10:46:32 +0100 | [diff] [blame] | 11 | #include <cortex_a57.h> |
Varun Wadekar | 25e658e | 2016-04-26 11:38:38 -0700 | [diff] [blame] | 12 | #include <platform_def.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 13 | #include <tegra_def.h> |
Harvey Hsieh | 6dc0d76 | 2017-04-24 19:35:51 +0800 | [diff] [blame] | 14 | #include <tegra_platform.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 15 | |
Varun Wadekar | b24dea9 | 2015-09-22 13:33:56 +0530 | [diff] [blame] | 16 | #define MIDR_PN_CORTEX_A57 0xD07 |
| 17 | |
| 18 | /******************************************************************************* |
| 19 | * Implementation defined ACTLR_EL3 bit definitions |
| 20 | ******************************************************************************/ |
Steven Kao | d417cea | 2017-06-14 14:02:23 +0800 | [diff] [blame] | 21 | #define ACTLR_EL3_L2ACTLR_BIT (U(1) << 6) |
| 22 | #define ACTLR_EL3_L2ECTLR_BIT (U(1) << 5) |
| 23 | #define ACTLR_EL3_L2CTLR_BIT (U(1) << 4) |
| 24 | #define ACTLR_EL3_CPUECTLR_BIT (U(1) << 1) |
| 25 | #define ACTLR_EL3_CPUACTLR_BIT (U(1) << 0) |
| 26 | #define ACTLR_EL3_ENABLE_ALL_MASK (ACTLR_EL3_L2ACTLR_BIT | \ |
| 27 | ACTLR_EL3_L2ECTLR_BIT | \ |
| 28 | ACTLR_EL3_L2CTLR_BIT | \ |
| 29 | ACTLR_EL3_CPUECTLR_BIT | \ |
| 30 | ACTLR_EL3_CPUACTLR_BIT) |
Varun Wadekar | b24dea9 | 2015-09-22 13:33:56 +0530 | [diff] [blame] | 31 | #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ |
Steven Kao | d417cea | 2017-06-14 14:02:23 +0800 | [diff] [blame] | 32 | ACTLR_EL3_L2ECTLR_BIT | \ |
| 33 | ACTLR_EL3_L2CTLR_BIT | \ |
| 34 | ACTLR_EL3_CPUECTLR_BIT | \ |
| 35 | ACTLR_EL3_CPUACTLR_BIT) |
Varun Wadekar | b24dea9 | 2015-09-22 13:33:56 +0530 | [diff] [blame] | 36 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 37 | /* Global functions */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 38 | .globl plat_is_my_cpu_primary |
| 39 | .globl plat_my_core_pos |
| 40 | .globl plat_get_my_entrypoint |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 41 | .globl plat_secondary_cold_boot_setup |
| 42 | .globl platform_mem_init |
| 43 | .globl plat_crash_console_init |
| 44 | .globl plat_crash_console_putc |
Antonio Nino Diaz | 1eb64a1 | 2018-10-17 15:29:34 +0100 | [diff] [blame] | 45 | .globl plat_crash_console_flush |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 46 | .globl tegra_secure_entrypoint |
| 47 | .globl plat_reset_handler |
| 48 | |
| 49 | /* Global variables */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 50 | .globl tegra_sec_entry_point |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 51 | .globl ns_image_entrypoint |
| 52 | .globl tegra_bl31_phys_base |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 53 | .globl tegra_console_base |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 54 | |
| 55 | /* --------------------- |
| 56 | * Common CPU init code |
| 57 | * --------------------- |
| 58 | */ |
| 59 | .macro cpu_init_common |
| 60 | |
Varun Wadekar | b24dea9 | 2015-09-22 13:33:56 +0530 | [diff] [blame] | 61 | /* ------------------------------------------------ |
Varun Wadekar | 69ce101 | 2016-05-12 13:43:33 -0700 | [diff] [blame] | 62 | * We enable procesor retention, L2/CPUECTLR NS |
| 63 | * access and ECC/Parity protection for A57 CPUs |
Varun Wadekar | b24dea9 | 2015-09-22 13:33:56 +0530 | [diff] [blame] | 64 | * ------------------------------------------------ |
| 65 | */ |
| 66 | mrs x0, midr_el1 |
| 67 | mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT) |
| 68 | and x0, x0, x1 |
| 69 | lsr x0, x0, #MIDR_PN_SHIFT |
| 70 | cmp x0, #MIDR_PN_CORTEX_A57 |
| 71 | b.ne 1f |
| 72 | |
Varun Wadekar | 4e9c231 | 2015-08-21 15:56:02 +0530 | [diff] [blame] | 73 | /* --------------------------- |
| 74 | * Enable processor retention |
| 75 | * --------------------------- |
Varun Wadekar | 69ce101 | 2016-05-12 13:43:33 -0700 | [diff] [blame] | 76 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 77 | mrs x0, CORTEX_A57_L2ECTLR_EL1 |
| 78 | mov x1, #RETENTION_ENTRY_TICKS_512 |
| 79 | bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK |
Varun Wadekar | 4e9c231 | 2015-08-21 15:56:02 +0530 | [diff] [blame] | 80 | orr x0, x0, x1 |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 81 | msr CORTEX_A57_L2ECTLR_EL1, x0 |
Varun Wadekar | 4e9c231 | 2015-08-21 15:56:02 +0530 | [diff] [blame] | 82 | isb |
Varun Wadekar | 4e9c231 | 2015-08-21 15:56:02 +0530 | [diff] [blame] | 83 | |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 84 | mrs x0, CORTEX_A57_ECTLR_EL1 |
| 85 | mov x1, #RETENTION_ENTRY_TICKS_512 |
| 86 | bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK |
Varun Wadekar | 4e9c231 | 2015-08-21 15:56:02 +0530 | [diff] [blame] | 87 | orr x0, x0, x1 |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 88 | msr CORTEX_A57_ECTLR_EL1, x0 |
Varun Wadekar | 4e9c231 | 2015-08-21 15:56:02 +0530 | [diff] [blame] | 89 | isb |
Varun Wadekar | 4e9c231 | 2015-08-21 15:56:02 +0530 | [diff] [blame] | 90 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 91 | /* ------------------------------------------------------- |
| 92 | * Enable L2 and CPU ECTLR RW access from non-secure world |
| 93 | * ------------------------------------------------------- |
Varun Wadekar | 69ce101 | 2016-05-12 13:43:33 -0700 | [diff] [blame] | 94 | */ |
Steven Kao | d417cea | 2017-06-14 14:02:23 +0800 | [diff] [blame] | 95 | mrs x0, actlr_el3 |
| 96 | mov x1, #ACTLR_EL3_ENABLE_ALL_MASK |
| 97 | bic x0, x0, x1 |
| 98 | mov x1, #ACTLR_EL3_ENABLE_ALL_ACCESS |
| 99 | orr x0, x0, x1 |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 100 | msr actlr_el3, x0 |
Steven Kao | d417cea | 2017-06-14 14:02:23 +0800 | [diff] [blame] | 101 | mrs x0, actlr_el2 |
| 102 | mov x1, #ACTLR_EL3_ENABLE_ALL_MASK |
| 103 | bic x0, x0, x1 |
| 104 | mov x1, #ACTLR_EL3_ENABLE_ALL_ACCESS |
| 105 | orr x0, x0, x1 |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 106 | msr actlr_el2, x0 |
| 107 | isb |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 108 | |
| 109 | /* -------------------------------- |
| 110 | * Enable the cycle count register |
| 111 | * -------------------------------- |
| 112 | */ |
Varun Wadekar | b24dea9 | 2015-09-22 13:33:56 +0530 | [diff] [blame] | 113 | 1: mrs x0, pmcr_el0 |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 114 | ubfx x0, x0, #11, #5 // read PMCR.N field |
| 115 | mov x1, #1 |
| 116 | lsl x0, x1, x0 |
| 117 | sub x0, x0, #1 // mask of event counters |
| 118 | orr x0, x0, #0x80000000 // disable overflow intrs |
| 119 | msr pmintenclr_el1, x0 |
| 120 | msr pmuserenr_el0, x1 // enable user mode access |
| 121 | |
| 122 | /* ---------------------------------------------------------------- |
| 123 | * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count |
| 124 | * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ |
| 125 | * registers from EL0. |
| 126 | * ---------------------------------------------------------------- |
| 127 | */ |
| 128 | mrs x0, cntkctl_el1 |
| 129 | orr x0, x0, #EL0VCTEN_BIT |
| 130 | msr cntkctl_el1, x0 |
| 131 | .endm |
| 132 | |
| 133 | /* ----------------------------------------------------- |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 134 | * unsigned int plat_is_my_cpu_primary(void); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 135 | * |
| 136 | * This function checks if this is the Primary CPU |
| 137 | * ----------------------------------------------------- |
| 138 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 139 | func plat_is_my_cpu_primary |
| 140 | mrs x0, mpidr_el1 |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 141 | and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) |
| 142 | cmp x0, #TEGRA_PRIMARY_CPU |
| 143 | cset x0, eq |
| 144 | ret |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 145 | endfunc plat_is_my_cpu_primary |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 146 | |
| 147 | /* ----------------------------------------------------- |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 148 | * unsigned int plat_my_core_pos(void); |
| 149 | * |
| 150 | * result: CorePos = CoreId + (ClusterId << 2) |
| 151 | * ----------------------------------------------------- |
| 152 | */ |
| 153 | func plat_my_core_pos |
| 154 | mrs x0, mpidr_el1 |
| 155 | and x1, x0, #MPIDR_CPU_MASK |
| 156 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 157 | add x0, x1, x0, LSR #6 |
| 158 | ret |
| 159 | endfunc plat_my_core_pos |
| 160 | |
| 161 | /* ----------------------------------------------------- |
| 162 | * unsigned long plat_get_my_entrypoint (void); |
| 163 | * |
| 164 | * Main job of this routine is to distinguish between |
| 165 | * a cold and warm boot. If the tegra_sec_entry_point for |
| 166 | * this CPU is present, then it's a warm boot. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 167 | * |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 168 | * ----------------------------------------------------- |
| 169 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 170 | func plat_get_my_entrypoint |
| 171 | adr x1, tegra_sec_entry_point |
| 172 | ldr x0, [x1] |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 173 | ret |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 174 | endfunc plat_get_my_entrypoint |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 175 | |
| 176 | /* ----------------------------------------------------- |
Varun Wadekar | 39f87d1 | 2015-09-22 13:45:07 +0530 | [diff] [blame] | 177 | * int platform_get_core_pos(int mpidr); |
| 178 | * |
| 179 | * With this function: CorePos = (ClusterId * 4) + |
| 180 | * CoreId |
| 181 | * ----------------------------------------------------- |
| 182 | */ |
| 183 | func platform_get_core_pos |
| 184 | and x1, x0, #MPIDR_CPU_MASK |
| 185 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 186 | add x0, x1, x0, LSR #6 |
| 187 | ret |
| 188 | endfunc platform_get_core_pos |
| 189 | |
| 190 | /* ----------------------------------------------------- |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 191 | * void plat_secondary_cold_boot_setup (void); |
| 192 | * |
| 193 | * This function performs any platform specific actions |
| 194 | * needed for a secondary cpu after a cold reset. Right |
| 195 | * now this is a stub function. |
| 196 | * ----------------------------------------------------- |
| 197 | */ |
| 198 | func plat_secondary_cold_boot_setup |
| 199 | mov x0, #0 |
| 200 | ret |
| 201 | endfunc plat_secondary_cold_boot_setup |
| 202 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 203 | /* -------------------------------------------------------- |
| 204 | * void platform_mem_init (void); |
| 205 | * |
| 206 | * Any memory init, relocation to be done before the |
| 207 | * platform boots. Called very early in the boot process. |
| 208 | * -------------------------------------------------------- |
| 209 | */ |
| 210 | func platform_mem_init |
| 211 | mov x0, #0 |
| 212 | ret |
| 213 | endfunc platform_mem_init |
| 214 | |
| 215 | /* --------------------------------------------- |
| 216 | * int plat_crash_console_init(void) |
| 217 | * Function to initialize the crash console |
| 218 | * without a C Runtime to print crash report. |
Juan Castillo | e7ae6db | 2015-11-26 14:52:15 +0000 | [diff] [blame] | 219 | * Clobber list : x0 - x4 |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 220 | * --------------------------------------------- |
| 221 | */ |
| 222 | func plat_crash_console_init |
Varun Wadekar | 4e6ae18 | 2017-04-04 13:40:12 -0700 | [diff] [blame] | 223 | mov x0, #0 |
| 224 | adr x1, tegra_console_base |
| 225 | ldr x1, [x1] |
| 226 | cbz x1, 1f |
| 227 | mov w0, #1 |
| 228 | 1: ret |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 229 | endfunc plat_crash_console_init |
| 230 | |
| 231 | /* --------------------------------------------- |
| 232 | * int plat_crash_console_putc(void) |
| 233 | * Function to print a character on the crash |
| 234 | * console without a C Runtime. |
| 235 | * Clobber list : x1, x2 |
| 236 | * --------------------------------------------- |
| 237 | */ |
| 238 | func plat_crash_console_putc |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 239 | adr x1, tegra_console_base |
| 240 | ldr x1, [x1] |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 241 | b console_core_putc |
| 242 | endfunc plat_crash_console_putc |
| 243 | |
Antonio Nino Diaz | 1eb64a1 | 2018-10-17 15:29:34 +0100 | [diff] [blame] | 244 | /* --------------------------------------------- |
| 245 | * int plat_crash_console_flush() |
| 246 | * Function to force a write of all buffered |
| 247 | * data that hasn't been output. |
| 248 | * Out : return -1 on error else return 0. |
| 249 | * Clobber list : x0, x1 |
| 250 | * --------------------------------------------- |
| 251 | */ |
| 252 | func plat_crash_console_flush |
| 253 | adr x0, tegra_console_base |
| 254 | ldr x0, [x0] |
| 255 | b console_core_flush |
| 256 | endfunc plat_crash_console_flush |
| 257 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 258 | /* --------------------------------------------------- |
| 259 | * Function to handle a platform reset and store |
| 260 | * input parameters passed by BL2. |
| 261 | * --------------------------------------------------- |
| 262 | */ |
| 263 | func plat_reset_handler |
| 264 | |
Varun Wadekar | 1ec441e | 2016-03-24 15:34:24 -0700 | [diff] [blame] | 265 | /* ---------------------------------------------------- |
| 266 | * Verify if we are running from BL31_BASE address |
| 267 | * ---------------------------------------------------- |
| 268 | */ |
| 269 | adr x18, bl31_entrypoint |
| 270 | mov x17, #BL31_BASE |
| 271 | cmp x18, x17 |
| 272 | b.eq 1f |
| 273 | |
| 274 | /* ---------------------------------------------------- |
| 275 | * Copy the entire BL31 code to BL31_BASE if we are not |
| 276 | * running from it already |
| 277 | * ---------------------------------------------------- |
| 278 | */ |
| 279 | mov x0, x17 |
| 280 | mov x1, x18 |
| 281 | mov x2, #BL31_SIZE |
| 282 | _loop16: |
| 283 | cmp x2, #16 |
Douglas Raillard | 2bb9f47 | 2017-03-20 10:38:29 +0000 | [diff] [blame] | 284 | b.lo _loop1 |
Varun Wadekar | 1ec441e | 2016-03-24 15:34:24 -0700 | [diff] [blame] | 285 | ldp x3, x4, [x1], #16 |
| 286 | stp x3, x4, [x0], #16 |
| 287 | sub x2, x2, #16 |
| 288 | b _loop16 |
| 289 | /* copy byte per byte */ |
| 290 | _loop1: |
| 291 | cbz x2, _end |
| 292 | ldrb w3, [x1], #1 |
| 293 | strb w3, [x0], #1 |
| 294 | subs x2, x2, #1 |
| 295 | b.ne _loop1 |
| 296 | |
| 297 | /* ---------------------------------------------------- |
| 298 | * Jump to BL31_BASE and start execution again |
| 299 | * ---------------------------------------------------- |
| 300 | */ |
| 301 | _end: mov x0, x20 |
| 302 | mov x1, x21 |
| 303 | br x17 |
| 304 | 1: |
| 305 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 306 | /* ----------------------------------- |
| 307 | * derive and save the phys_base addr |
| 308 | * ----------------------------------- |
| 309 | */ |
| 310 | adr x17, tegra_bl31_phys_base |
| 311 | ldr x18, [x17] |
| 312 | cbnz x18, 1f |
| 313 | adr x18, bl31_entrypoint |
| 314 | str x18, [x17] |
| 315 | |
| 316 | 1: cpu_init_common |
| 317 | |
| 318 | ret |
| 319 | endfunc plat_reset_handler |
| 320 | |
| 321 | /* ---------------------------------------- |
| 322 | * Secure entrypoint function for CPU boot |
| 323 | * ---------------------------------------- |
| 324 | */ |
Julius Werner | b4c75e9 | 2017-08-01 15:16:36 -0700 | [diff] [blame] | 325 | func tegra_secure_entrypoint _align=6 |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 326 | |
| 327 | #if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT |
| 328 | |
Harvey Hsieh | 6dc0d76 | 2017-04-24 19:35:51 +0800 | [diff] [blame] | 329 | /* -------------------------------------------------------- |
| 330 | * Skip the invalidate BTB workaround for Tegra210B01 SKUs. |
| 331 | * -------------------------------------------------------- |
| 332 | */ |
| 333 | mov x0, #TEGRA_MISC_BASE |
| 334 | add x0, x0, #HARDWARE_REVISION_OFFSET |
| 335 | ldr w1, [x0] |
| 336 | lsr w1, w1, #CHIP_ID_SHIFT |
| 337 | and w1, w1, #CHIP_ID_MASK |
| 338 | cmp w1, #TEGRA_CHIPID_TEGRA21 /* T210? */ |
| 339 | b.ne 2f |
| 340 | ldr w1, [x0] |
| 341 | lsr w1, w1, #MAJOR_VERSION_SHIFT |
| 342 | and w1, w1, #MAJOR_VERSION_MASK |
| 343 | cmp w1, #0x02 /* T210 B01? */ |
| 344 | b.eq 2f |
| 345 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 346 | /* ------------------------------------------------------- |
| 347 | * Invalidate BTB along with I$ to remove any stale |
| 348 | * entries from the branch predictor array. |
| 349 | * ------------------------------------------------------- |
| 350 | */ |
Eleanor Bonnici | 91b11c3 | 2017-08-10 14:46:26 +0100 | [diff] [blame] | 351 | mrs x0, CORTEX_A57_CPUACTLR_EL1 |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 352 | orr x0, x0, #1 |
Eleanor Bonnici | 91b11c3 | 2017-08-10 14:46:26 +0100 | [diff] [blame] | 353 | msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 354 | dsb sy |
| 355 | isb |
| 356 | ic iallu /* actual invalidate */ |
| 357 | dsb sy |
| 358 | isb |
| 359 | |
Eleanor Bonnici | 91b11c3 | 2017-08-10 14:46:26 +0100 | [diff] [blame] | 360 | mrs x0, CORTEX_A57_CPUACTLR_EL1 |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 361 | bic x0, x0, #1 |
Eleanor Bonnici | 91b11c3 | 2017-08-10 14:46:26 +0100 | [diff] [blame] | 362 | msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 363 | dsb sy |
| 364 | isb |
| 365 | |
| 366 | .rept 7 |
| 367 | nop /* wait */ |
| 368 | .endr |
| 369 | |
| 370 | /* ----------------------------------------------- |
| 371 | * Extract OSLK bit and check if it is '1'. This |
| 372 | * bit remains '0' for A53 on warm-resets. If '1', |
| 373 | * turn off regional clock gating and request warm |
| 374 | * reset. |
| 375 | * ----------------------------------------------- |
| 376 | */ |
| 377 | mrs x0, oslsr_el1 |
| 378 | and x0, x0, #2 |
| 379 | mrs x1, mpidr_el1 |
| 380 | bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */ |
| 381 | b.eq restore_oslock |
| 382 | mov x0, xzr |
| 383 | msr oslar_el1, x0 /* os lock stays 0 across warm reset */ |
| 384 | mov x3, #3 |
| 385 | movz x4, #0x8000, lsl #48 |
Eleanor Bonnici | 91b11c3 | 2017-08-10 14:46:26 +0100 | [diff] [blame] | 386 | msr CORTEX_A57_CPUACTLR_EL1, x4 /* turn off RCG */ |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 387 | isb |
| 388 | msr rmr_el3, x3 /* request warm reset */ |
| 389 | isb |
| 390 | dsb sy |
| 391 | 1: wfi |
| 392 | b 1b |
| 393 | |
| 394 | /* -------------------------------------------------- |
| 395 | * These nops are here so that speculative execution |
| 396 | * won't harm us before we are done with warm reset. |
| 397 | * -------------------------------------------------- |
| 398 | */ |
| 399 | .rept 65 |
| 400 | nop |
| 401 | .endr |
Harvey Hsieh | 6dc0d76 | 2017-04-24 19:35:51 +0800 | [diff] [blame] | 402 | 2: |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 403 | /* -------------------------------------------------- |
| 404 | * Do not insert instructions here |
| 405 | * -------------------------------------------------- |
| 406 | */ |
| 407 | #endif |
| 408 | |
| 409 | /* -------------------------------------------------- |
| 410 | * Restore OS Lock bit |
| 411 | * -------------------------------------------------- |
| 412 | */ |
| 413 | restore_oslock: |
| 414 | mov x0, #1 |
| 415 | msr oslar_el1, x0 |
| 416 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 417 | /* -------------------------------------------------- |
| 418 | * Get secure world's entry point and jump to it |
| 419 | * -------------------------------------------------- |
| 420 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 421 | bl plat_get_my_entrypoint |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 422 | br x0 |
| 423 | endfunc tegra_secure_entrypoint |
| 424 | |
| 425 | .data |
| 426 | .align 3 |
| 427 | |
| 428 | /* -------------------------------------------------- |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 429 | * CPU Secure entry point - resume from suspend |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 430 | * -------------------------------------------------- |
| 431 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 432 | tegra_sec_entry_point: |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 433 | .quad 0 |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 434 | |
| 435 | /* -------------------------------------------------- |
| 436 | * NS world's cold boot entry point |
| 437 | * -------------------------------------------------- |
| 438 | */ |
| 439 | ns_image_entrypoint: |
| 440 | .quad 0 |
| 441 | |
| 442 | /* -------------------------------------------------- |
| 443 | * BL31's physical base address |
| 444 | * -------------------------------------------------- |
| 445 | */ |
| 446 | tegra_bl31_phys_base: |
| 447 | .quad 0 |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 448 | |
| 449 | /* -------------------------------------------------- |
| 450 | * UART controller base for console init |
| 451 | * -------------------------------------------------- |
| 452 | */ |
| 453 | tegra_console_base: |
| 454 | .quad 0 |