| developer | 2189d3a | 2020-04-17 17:14:23 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /* Project Includes */ |
| 8 | #include <arch.h> |
| 9 | #include <arch_helpers.h> |
| 10 | #include <lib/psci/psci.h> |
| 11 | |
| 12 | /* Platform Includes */ |
| 13 | #include <plat_helpers.h> |
| 14 | #include <platform_def.h> |
| 15 | |
| 16 | const unsigned char mtk_power_domain_tree_desc[] = { |
| 17 | /* Number of root nodes */ |
| 18 | PLATFORM_SYSTEM_COUNT, |
| 19 | /* Number of children for the root node */ |
| 20 | PLATFORM_CLUSTER_COUNT, |
| 21 | /* Number of children for the first cluster node */ |
| 22 | PLATFORM_CLUSTER0_CORE_COUNT, |
| 23 | }; |
| 24 | |
| 25 | /******************************************************************************* |
| 26 | * This function returns the MT8192 default topology tree information. |
| 27 | ******************************************************************************/ |
| 28 | const unsigned char *plat_get_power_domain_tree_desc(void) |
| 29 | { |
| 30 | return mtk_power_domain_tree_desc; |
| 31 | } |
| 32 | |
| 33 | /******************************************************************************* |
| 34 | * This function implements a part of the critical interface between the psci |
| 35 | * generic layer and the platform that allows the former to query the platform |
| 36 | * to convert an MPIDR to a unique linear index. An error code (-1) is returned |
| 37 | * in case the MPIDR is invalid. |
| 38 | ******************************************************************************/ |
| 39 | int plat_core_pos_by_mpidr(u_register_t mpidr) |
| 40 | { |
| 41 | unsigned int cluster_id, cpu_id; |
| 42 | |
| 43 | if (read_mpidr() & MPIDR_MT_MASK) { |
| 44 | /* ARMv8.2 arch */ |
| 45 | if (mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) { |
| 46 | return -1; |
| 47 | } |
| 48 | return plat_mediatek_calc_core_pos(mpidr); |
| 49 | } |
| 50 | |
| 51 | mpidr &= MPIDR_AFFINITY_MASK; |
| 52 | |
| 53 | if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { |
| 54 | return -1; |
| 55 | } |
| 56 | |
| 57 | cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; |
| 58 | cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; |
| 59 | |
| 60 | if (cluster_id >= PLATFORM_CLUSTER_COUNT) { |
| 61 | return -1; |
| 62 | } |
| 63 | |
| 64 | /* |
| 65 | * Validate cpu_id by checking whether it represents a CPU in |
| 66 | * one of the two clusters present on the platform. |
| 67 | */ |
| 68 | if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) { |
| 69 | return -1; |
| 70 | } |
| 71 | |
| 72 | return (cpu_id + (cluster_id * 8)); |
| 73 | } |