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Jiafei Pana07047b2022-02-18 15:27:45 +08001/*
2 * Copyright 2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLAT_DEF_H
8#define PLAT_DEF_H
9
10#include <arch.h>
11/*
12 * Required without TBBR.
13 * To include the defines for DDR PHY
14 * Images.
15 */
16#include <tbbr_img_def.h>
17
18#include <policy.h>
19#include <soc.h>
20
21#define NXP_SPD_EEPROM0 0x51
22
23#define NXP_SYSCLK_FREQ 100000000
24#define NXP_DDRCLK_FREQ 100000000
25
26/* UART related definition */
27#define NXP_CONSOLE_ADDR NXP_UART_ADDR
28#define NXP_CONSOLE_BAUDRATE 115200
29
30/* Size of cacheable stacks */
31#if defined(IMAGE_BL2)
32#if defined(TRUSTED_BOARD_BOOT)
33#define PLATFORM_STACK_SIZE 0x2000
34#else
35#define PLATFORM_STACK_SIZE 0x1000
36#endif
37#elif defined(IMAGE_BL31)
38#define PLATFORM_STACK_SIZE 0x1000
39#endif
40
41#define BL2_START NXP_OCRAM_ADDR
42#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
43#define BL2_NOLOAD_START NXP_OCRAM_ADDR
44#define BL2_NOLOAD_LIMIT BL2_BASE
45
46/* IO defines as needed by IO driver framework */
47#define MAX_IO_DEVICES 4
48#define MAX_IO_BLOCK_DEVICES 1
49#define MAX_IO_HANDLES 4
50
51/*
52 * FIP image defines - Offset at which FIP Image would be present
53 * Image would include Bl31 , Bl33 and Bl32 (optional)
54 */
55#ifdef POLICY_FUSE_PROVISION
56#define MAX_FIP_DEVICES 2
57#endif
58
59#ifndef MAX_FIP_DEVICES
60#define MAX_FIP_DEVICES 1
61#endif
62
63#define BL32_IRQ_SEC_PHY_TIMER 29
64#define BL31_WDOG_SEC 89
65
66/*
67 * ID of the secure physical generic timer interrupt used by the BL32.
68 */
69#define PLAT_LS_G1S_IRQ_PROPS(grp) \
70 INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
71 GIC_INTR_CFG_LEVEL)
72
73/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
74#define PLAT_LS_G0_IRQ_PROPS(grp) \
75 INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
76 GIC_INTR_CFG_EDGE), \
77 INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \
78 GIC_INTR_CFG_LEVEL)
79
80
81#endif /* PLAT_DEF_H */