| Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 1 | /* |
| Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
| Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __SMMU_V3_H__ |
| 8 | #define __SMMU_V3_H__ |
| 9 | |
| Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 10 | #include <utils_def.h> |
| Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 11 | #include <stdint.h> |
| 12 | |
| 13 | /* SMMUv3 register offsets from device base */ |
| Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 14 | #define SMMU_S_IDR1 U(0x8004) |
| 15 | #define SMMU_S_INIT U(0x803c) |
| Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 16 | |
| 17 | /* SMMU_S_IDR1 register fields */ |
| 18 | #define SMMU_S_IDR1_SECURE_IMPL_SHIFT 31 |
| Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 19 | #define SMMU_S_IDR1_SECURE_IMPL_MASK U(0x1) |
| Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 20 | |
| 21 | /* SMMU_S_INIT register fields */ |
| Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 22 | #define SMMU_S_INIT_INV_ALL_MASK U(0x1) |
| Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 23 | |
| 24 | |
| 25 | int smmuv3_init(uintptr_t smmu_base); |
| 26 | |
| 27 | #endif /* __SMMU_V3_H__ */ |