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Antonio Nino Diaz493bf332016-12-14 14:31:32 +00001#
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -07002# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
Jeremie Corbier9e1873f2021-09-07 11:49:58 +02003# Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
Akshay Belsareec0afc82023-02-27 12:04:26 +05304# Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
5# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08006#
dp-armfa3cf0b2017-05-03 09:38:09 +01007# SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08008
Soren Brinkmannba8309d2017-04-06 11:44:27 -07009override ERRATA_A53_855873 := 1
Michal Simek81ec0d12023-02-09 13:21:10 +010010ERRATA_A53_1530924 := 1
Masahiro Yamada8cf895c2016-12-19 17:41:47 +090011override PROGRAMMABLE_RESET_ADDRESS := 1
Soren Brinkmann76fcae32016-03-06 20:16:27 -080012PSCI_EXTENDED_STATE_ID := 1
13A53_DISABLE_NON_TEMPORAL_HINT := 0
Soren Brinkmann6d1ba582016-07-08 14:45:14 -070014SEPARATE_CODE_AND_RODATA := 1
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +053015ZYNQMP_WDT_RESTART := 0
Venkatesh Yadav Abbarapubfa2a2a2021-02-19 01:40:14 -070016IPI_CRC_CHECK := 0
Masahiro Yamada8cf895c2016-12-19 17:41:47 +090017override RESET_TO_BL31 := 1
Siva Durga Prasad Paladugu60bfbc92018-09-24 22:51:49 -070018override WARMBOOT_ENABLE_DCACHE_EARLY := 1
Soren Brinkmann76fcae32016-03-06 20:16:27 -080019
Jan Kiszkae1407fc2020-07-14 22:36:59 +020020EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
21
Jeremie Corbier9e1873f2021-09-07 11:49:58 +020022# pncd SPD requires secure SGI to be handled at EL1
23ifeq (${SPD},pncd)
24ifeq (${ZYNQMP_WDT_RESTART},1)
25$(error "Error: ZYNQMP_WDT_RESTART and SPD=pncd are incompatible")
26endif
27override GICV2_G0_FOR_EL3 := 0
28else
29override GICV2_G0_FOR_EL3 := 1
30endif
31
David Cunadoc5b0c0f2017-10-31 23:19:21 +000032# Do not enable SVE
33ENABLE_SVE_FOR_NS := 0
34
Dimitris Papastamos8e5bd5e2018-01-24 16:41:14 +000035WORKAROUND_CVE_2017_5715 := 0
36
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +053037ARM_XLAT_TABLES_LIB_V1 := 1
Venkatesh Yadav Abbarapu6d7f1e82022-05-06 14:07:15 +053038$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
39$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
40
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070041ifdef ZYNQMP_ATF_MEM_BASE
42 $(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))
43
44 ifndef ZYNQMP_ATF_MEM_SIZE
45 $(error "ZYNQMP_ATF_BASE defined without ZYNQMP_ATF_SIZE")
46 endif
47 $(eval $(call add_define,ZYNQMP_ATF_MEM_SIZE))
Soren Brinkmann76fcae32016-03-06 20:16:27 -080048
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070049 ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
50 $(eval $(call add_define,ZYNQMP_ATF_MEM_PROGBITS_SIZE))
51 endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -080052endif
53
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070054ifdef ZYNQMP_BL32_MEM_BASE
55 $(eval $(call add_define,ZYNQMP_BL32_MEM_BASE))
56
57 ifndef ZYNQMP_BL32_MEM_SIZE
58 $(error "ZYNQMP_BL32_BASE defined without ZYNQMP_BL32_SIZE")
59 endif
60 $(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE))
61endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -080062
Soren Brinkmann99c0d7b2016-06-10 09:57:14 -070063
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +053064ifdef ZYNQMP_WDT_RESTART
Michal Simek08341b72022-03-09 08:53:20 +010065 $(eval $(call add_define,ZYNQMP_WDT_RESTART))
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +053066endif
67
Venkatesh Yadav Abbarapu35a8be92019-04-04 14:23:32 +053068ifdef ZYNQMP_IPI_CRC_CHECK
Michal Simek08341b72022-03-09 08:53:20 +010069 $(warning "ZYNQMP_IPI_CRC_CHECK macro is deprecated...instead please use IPI_CRC_CHECK.")
Venkatesh Yadav Abbarapubfa2a2a2021-02-19 01:40:14 -070070endif
71
72ifdef IPI_CRC_CHECK
73 $(eval $(call add_define,IPI_CRC_CHECK))
Venkatesh Yadav Abbarapu35a8be92019-04-04 14:23:32 +053074endif
75
Vesa Jääskeläinen28f9ce52022-04-29 08:47:24 +030076ifdef ZYNQMP_SECURE_EFUSES
77 $(eval $(call add_define,ZYNQMP_SECURE_EFUSES))
78endif
79
Akshay Belsareec0afc82023-02-27 12:04:26 +053080ifdef XILINX_OF_BOARD_DTB_ADDR
81$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
82endif
83
Venkatesh Yadav Abbarapu35a8be92019-04-04 14:23:32 +053084PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
85 -Iinclude/plat/arm/common/aarch64/ \
Jolly Shahb07fd0c2019-01-08 11:25:28 -080086 -Iplat/xilinx/common/include/ \
Wendy Liangc31c48b2019-01-21 13:45:48 +053087 -Iplat/xilinx/common/ipi_mailbox_service/ \
Soren Brinkmann76fcae32016-03-06 20:16:27 -080088 -Iplat/xilinx/zynqmp/include/ \
Wendy Liangf8fec362017-09-06 09:39:55 -070089 -Iplat/xilinx/zynqmp/pm_service/ \
Soren Brinkmann76fcae32016-03-06 20:16:27 -080090
Michal Simek53865b02021-05-27 09:42:37 +020091include lib/libfdt/libfdt.mk
Venkatesh Yadav Abbarapu1ad5f662020-12-03 20:27:18 -070092# Include GICv2 driver files
93include drivers/arm/gic/v2/gicv2.mk
94
Soby Mathewcc037c12016-04-08 16:42:58 +010095PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
96 lib/xlat_tables/aarch64/xlat_tables.c \
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -070097 drivers/arm/dcc/dcc_console.c \
Soren Brinkmanne5bdcaa2016-06-22 09:02:56 -070098 drivers/delay_timer/delay_timer.c \
99 drivers/delay_timer/generic_delay_timer.c \
Venkatesh Yadav Abbarapu1ad5f662020-12-03 20:27:18 -0700100 ${GICV2_SOURCES} \
Soby Mathew17231132016-08-08 12:33:06 +0100101 drivers/cadence/uart/aarch64/cdns_console.S \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800102 plat/arm/common/arm_cci.c \
Soby Mathew0eb965b2016-07-07 08:45:56 +0100103 plat/arm/common/arm_common.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800104 plat/arm/common/arm_gicv2.c \
105 plat/common/plat_gicv2.c \
Jolly Shahc2583ab2019-01-08 11:31:49 -0800106 plat/xilinx/common/ipi.c \
Venkatesh Yadav Abbarapu44e563a2021-01-23 22:16:47 -0700107 plat/xilinx/zynqmp/zynqmp_ipi.c \
108 plat/common/aarch64/crash_console_helpers.S \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800109 plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \
110 plat/xilinx/zynqmp/aarch64/zynqmp_common.c
111
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -0700112ZYNQMP_CONSOLE ?= cadence
113ifeq (${ZYNQMP_CONSOLE}, $(filter ${ZYNQMP_CONSOLE},cadence cadence0 cadence1 dcc))
114else
115 $(error "Please define ZYNQMP_CONSOLE")
116endif
117$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE}))
118
Amit Nagal20f7afc2023-03-23 14:16:01 +0530119# Build PM code as a Library
120include plat/xilinx/zynqmp/libpm.mk
121
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800122BL31_SOURCES += drivers/arm/cci/cci.c \
123 lib/cpus/aarch64/aem_generic.S \
124 lib/cpus/aarch64/cortex_a53.S \
Soby Mathewf6c41082016-05-03 12:31:18 +0100125 plat/common/plat_psci_common.c \
Michal Simek53865b02021-05-27 09:42:37 +0200126 common/fdt_fixup.c \
127 ${LIBFDT_SRCS} \
Wendy Liangc31c48b2019-01-21 13:45:48 +0530128 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -0700129 plat/xilinx/common/plat_startup.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800130 plat/xilinx/zynqmp/bl31_zynqmp_setup.c \
131 plat/xilinx/zynqmp/plat_psci.c \
132 plat/xilinx/zynqmp/plat_zynqmp.c \
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800133 plat/xilinx/zynqmp/plat_topology.c \
Amit Nagal20f7afc2023-03-23 14:16:01 +0530134 plat/xilinx/zynqmp/sip_svc_setup.c
Wendy Liangc31c48b2019-01-21 13:45:48 +0530135
Jan Kiszkae1407fc2020-07-14 22:36:59 +0200136ifeq (${SDEI_SUPPORT},1)
137BL31_SOURCES += plat/xilinx/zynqmp/zynqmp_ehf.c \
138 plat/xilinx/zynqmp/zynqmp_sdei.c
139endif
140
Venkatesh Yadav Abbarapu2dfbba42020-07-13 21:18:01 -0600141BL31_CPPFLAGS += -fno-jump-tables
Venkatesh Yadav Abbarapuf9d518a2021-12-06 21:28:34 -0700142TF_CFLAGS_aarch64 += -mbranch-protection=none
Venkatesh Yadav Abbarapu2dfbba42020-07-13 21:18:01 -0600143
Amit Nagalf7ecba32023-02-15 18:43:55 +0530144ifdef CUSTOM_PKG_PATH
145include $(CUSTOM_PKG_PATH)/custom_pkg.mk
146else
147BL31_SOURCES += plat/xilinx/zynqmp/custom_sip_svc.c
148endif
149
Wendy Liangc31c48b2019-01-21 13:45:48 +0530150ifneq (${RESET_TO_BL31},1)
151 $(error "Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1.")
152endif