| Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 1 | # |
| 2 | # Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. |
| 3 | # |
| 4 | # SPDX-License-Identifier: BSD-3-Clause |
| 5 | # |
| 6 | |
| 7 | RESET_TO_BL31 := 1 |
| 8 | ifeq (${RESET_TO_BL31}, 0) |
| 9 | $(error "This is a BL31-only port; RESET_TO_BL31 must be enabled") |
| 10 | endif |
| 11 | |
| 12 | CTX_INCLUDE_AARCH32_REGS := 0 |
| 13 | ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) |
| 14 | $(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") |
| 15 | endif |
| 16 | |
| 17 | ifeq (${TRUSTED_BOARD_BOOT}, 1) |
| 18 | $(error "TRUSTED_BOARD_BOOT must be disabled") |
| 19 | endif |
| 20 | |
| 21 | ifndef PRELOADED_BL33_BASE |
| 22 | $(error "PRELOADED_BL33_BASE is not set") |
| 23 | endif |
| 24 | |
| 25 | ifndef FPGA_PRELOADED_DTB_BASE |
| 26 | $(error "FPGA_PRELOADED_DTB_BASE is not set") |
| 27 | else |
| 28 | $(eval $(call add_define,FPGA_PRELOADED_DTB_BASE)) |
| 29 | endif |
| 30 | |
| 31 | # Treating this as a memory-constrained port for now |
| 32 | USE_COHERENT_MEM := 0 |
| 33 | |
| 34 | # The CPU in the initial image makes use of this feature |
| 35 | HW_ASSISTED_COHERENCY := 1 |
| 36 | |
| 37 | FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S \ |
| 38 | lib/cpus/aarch64/neoverse_zeus.S |
| 39 | |
| 40 | FPGA_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ |
| 41 | drivers/arm/gic/v3/gicv3_main.c \ |
| 42 | plat/common/plat_gicv3.c |
| 43 | |
| 44 | PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include |
| 45 | |
| 46 | PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S |
| 47 | |
| 48 | BL31_SOURCES += drivers/delay_timer/delay_timer.c \ |
| 49 | drivers/delay_timer/generic_delay_timer.c \ |
| 50 | drivers/arm/pl011/${ARCH}/pl011_console.S \ |
| 51 | plat/common/plat_psci_common.c \ |
| 52 | plat/arm/board/arm_fpga/fpga_pm.c \ |
| 53 | plat/arm/board/arm_fpga/fpga_topology.c \ |
| 54 | plat/arm/board/arm_fpga/fpga_console.c \ |
| 55 | plat/arm/board/arm_fpga/fpga_bl31_setup.c \ |
| 56 | ${FPGA_CPU_LIBS} \ |
| 57 | ${FPGA_GIC_SOURCES} |
| 58 | |
| 59 | all: bl31 |