Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013, ARM Limited. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | |
| 33 | .globl enable_irq |
| 34 | .globl disable_irq |
| 35 | |
| 36 | .globl enable_fiq |
| 37 | .globl disable_fiq |
| 38 | |
| 39 | .globl enable_serror |
| 40 | .globl disable_serror |
| 41 | |
| 42 | .globl read_daif |
| 43 | .globl write_daif |
| 44 | |
| 45 | .globl read_spsr |
| 46 | .globl read_spsr_el1 |
| 47 | .globl read_spsr_el2 |
| 48 | .globl read_spsr_el3 |
| 49 | |
| 50 | .globl write_spsr |
| 51 | .globl write_spsr_el1 |
| 52 | .globl write_spsr_el2 |
| 53 | .globl write_spsr_el3 |
| 54 | |
| 55 | .globl read_elr |
| 56 | .globl read_elr_el1 |
| 57 | .globl read_elr_el2 |
| 58 | .globl read_elr_el3 |
| 59 | |
| 60 | .globl write_elr |
| 61 | .globl write_elr_el1 |
| 62 | .globl write_elr_el2 |
| 63 | .globl write_elr_el3 |
| 64 | |
| 65 | .globl get_afflvl_shift |
| 66 | .globl mpidr_mask_lower_afflvls |
| 67 | .globl dsb |
| 68 | .globl isb |
| 69 | .globl sev |
| 70 | .globl wfe |
| 71 | .globl wfi |
| 72 | .globl eret |
| 73 | .globl smc |
| 74 | |
| 75 | |
| 76 | .section .text, "ax" |
| 77 | |
| 78 | get_afflvl_shift:; .type get_afflvl_shift, %function |
| 79 | cmp x0, #3 |
| 80 | cinc x0, x0, eq |
| 81 | mov x1, #MPIDR_AFFLVL_SHIFT |
| 82 | lsl x0, x0, x1 |
| 83 | ret |
| 84 | |
| 85 | mpidr_mask_lower_afflvls:; .type mpidr_mask_lower_afflvls, %function |
| 86 | cmp x1, #3 |
| 87 | cinc x1, x1, eq |
| 88 | mov x2, #MPIDR_AFFLVL_SHIFT |
| 89 | lsl x2, x1, x2 |
| 90 | lsr x0, x0, x2 |
| 91 | lsl x0, x0, x2 |
| 92 | ret |
| 93 | |
| 94 | /* ----------------------------------------------------- |
| 95 | * Asynchronous exception manipulation accessors |
| 96 | * ----------------------------------------------------- |
| 97 | */ |
| 98 | enable_irq:; .type enable_irq, %function |
| 99 | msr daifclr, #DAIF_IRQ_BIT |
| 100 | ret |
| 101 | |
| 102 | |
| 103 | enable_fiq:; .type enable_fiq, %function |
| 104 | msr daifclr, #DAIF_FIQ_BIT |
| 105 | ret |
| 106 | |
| 107 | |
| 108 | enable_serror:; .type enable_serror, %function |
| 109 | msr daifclr, #DAIF_ABT_BIT |
| 110 | ret |
| 111 | |
| 112 | |
| 113 | disable_irq:; .type disable_irq, %function |
| 114 | msr daifset, #DAIF_IRQ_BIT |
| 115 | ret |
| 116 | |
| 117 | |
| 118 | disable_fiq:; .type disable_fiq, %function |
| 119 | msr daifset, #DAIF_FIQ_BIT |
| 120 | ret |
| 121 | |
| 122 | |
| 123 | disable_serror:; .type disable_serror, %function |
| 124 | msr daifset, #DAIF_ABT_BIT |
| 125 | ret |
| 126 | |
| 127 | |
| 128 | read_daif:; .type read_daif, %function |
| 129 | mrs x0, daif |
| 130 | ret |
| 131 | |
| 132 | |
| 133 | write_daif:; .type write_daif, %function |
| 134 | msr daif, x0 |
| 135 | ret |
| 136 | |
| 137 | |
| 138 | read_spsr:; .type read_spsr, %function |
| 139 | mrs x0, CurrentEl |
| 140 | cmp x0, #(MODE_EL1 << MODE_EL_SHIFT) |
| 141 | b.eq read_spsr_el1 |
| 142 | cmp x0, #(MODE_EL2 << MODE_EL_SHIFT) |
| 143 | b.eq read_spsr_el2 |
| 144 | cmp x0, #(MODE_EL3 << MODE_EL_SHIFT) |
| 145 | b.eq read_spsr_el3 |
| 146 | |
| 147 | |
| 148 | read_spsr_el1:; .type read_spsr_el1, %function |
| 149 | mrs x0, spsr_el1 |
| 150 | ret |
| 151 | |
| 152 | |
| 153 | read_spsr_el2:; .type read_spsr_el2, %function |
| 154 | mrs x0, spsr_el2 |
| 155 | ret |
| 156 | |
| 157 | |
| 158 | read_spsr_el3:; .type read_spsr_el3, %function |
| 159 | mrs x0, spsr_el3 |
| 160 | ret |
| 161 | |
| 162 | |
| 163 | write_spsr:; .type write_spsr, %function |
| 164 | mrs x1, CurrentEl |
| 165 | cmp x1, #(MODE_EL1 << MODE_EL_SHIFT) |
| 166 | b.eq write_spsr_el1 |
| 167 | cmp x1, #(MODE_EL2 << MODE_EL_SHIFT) |
| 168 | b.eq write_spsr_el2 |
| 169 | cmp x1, #(MODE_EL3 << MODE_EL_SHIFT) |
| 170 | b.eq write_spsr_el3 |
| 171 | |
| 172 | |
| 173 | write_spsr_el1:; .type write_spsr_el1, %function |
| 174 | msr spsr_el1, x0 |
| 175 | isb |
| 176 | ret |
| 177 | |
| 178 | |
| 179 | write_spsr_el2:; .type write_spsr_el2, %function |
| 180 | msr spsr_el2, x0 |
| 181 | isb |
| 182 | ret |
| 183 | |
| 184 | |
| 185 | write_spsr_el3:; .type write_spsr_el3, %function |
| 186 | msr spsr_el3, x0 |
| 187 | isb |
| 188 | ret |
| 189 | |
| 190 | |
| 191 | read_elr:; .type read_elr, %function |
| 192 | mrs x0, CurrentEl |
| 193 | cmp x0, #(MODE_EL1 << MODE_EL_SHIFT) |
| 194 | b.eq read_elr_el1 |
| 195 | cmp x0, #(MODE_EL2 << MODE_EL_SHIFT) |
| 196 | b.eq read_elr_el2 |
| 197 | cmp x0, #(MODE_EL3 << MODE_EL_SHIFT) |
| 198 | b.eq read_elr_el3 |
| 199 | |
| 200 | |
| 201 | read_elr_el1:; .type read_elr_el1, %function |
| 202 | mrs x0, elr_el1 |
| 203 | ret |
| 204 | |
| 205 | |
| 206 | read_elr_el2:; .type read_elr_el2, %function |
| 207 | mrs x0, elr_el2 |
| 208 | ret |
| 209 | |
| 210 | |
| 211 | read_elr_el3:; .type read_elr_el3, %function |
| 212 | mrs x0, elr_el3 |
| 213 | ret |
| 214 | |
| 215 | |
| 216 | write_elr:; .type write_elr, %function |
| 217 | mrs x1, CurrentEl |
| 218 | cmp x1, #(MODE_EL1 << MODE_EL_SHIFT) |
| 219 | b.eq write_elr_el1 |
| 220 | cmp x1, #(MODE_EL2 << MODE_EL_SHIFT) |
| 221 | b.eq write_elr_el2 |
| 222 | cmp x1, #(MODE_EL3 << MODE_EL_SHIFT) |
| 223 | b.eq write_elr_el3 |
| 224 | |
| 225 | |
| 226 | write_elr_el1:; .type write_elr_el1, %function |
| 227 | msr elr_el1, x0 |
| 228 | isb |
| 229 | ret |
| 230 | |
| 231 | |
| 232 | write_elr_el2:; .type write_elr_el2, %function |
| 233 | msr elr_el2, x0 |
| 234 | isb |
| 235 | ret |
| 236 | |
| 237 | |
| 238 | write_elr_el3:; .type write_elr_el3, %function |
| 239 | msr elr_el3, x0 |
| 240 | isb |
| 241 | ret |
| 242 | |
| 243 | |
| 244 | dsb:; .type dsb, %function |
| 245 | dsb sy |
| 246 | ret |
| 247 | |
| 248 | |
| 249 | isb:; .type isb, %function |
| 250 | isb |
| 251 | ret |
| 252 | |
| 253 | |
| 254 | sev:; .type sev, %function |
| 255 | sev |
| 256 | ret |
| 257 | |
| 258 | |
| 259 | wfe:; .type wfe, %function |
| 260 | wfe |
| 261 | ret |
| 262 | |
| 263 | |
| 264 | wfi:; .type wfi, %function |
| 265 | wfi |
| 266 | ret |
| 267 | |
| 268 | |
| 269 | eret:; .type eret, %function |
| 270 | eret |
| 271 | |
| 272 | |
| 273 | smc:; .type smc, %function |
| 274 | smc #0 |