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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010033
34/*******************************************************************************
35 * Function that does the first bit of architectural setup that affects
36 * execution in the non-secure address space.
37 ******************************************************************************/
38void bl1_arch_setup(void)
39{
Achin Guptaed1744e2014-08-04 23:13:10 +010040 /* Set the next EL to be AArch64 */
41 write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT);
Achin Gupta4f6ad662013-10-25 09:08:21 +010042}
43
44/*******************************************************************************
45 * Set the Secure EL1 required architectural state
46 ******************************************************************************/
Juan Castillo2d552402014-06-13 17:05:10 +010047void bl1_arch_next_el_setup(void)
48{
Vikram Kanigiri78a6e0c2014-03-11 17:41:00 +000049 unsigned long next_sctlr;
Achin Gupta4f6ad662013-10-25 09:08:21 +010050
51 /* Use the same endianness than the current BL */
Vikram Kanigiri78a6e0c2014-03-11 17:41:00 +000052 next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT);
Achin Gupta4f6ad662013-10-25 09:08:21 +010053
54 /* Set SCTLR Secure EL1 */
55 next_sctlr |= SCTLR_EL1_RES1;
56
57 write_sctlr_el1(next_sctlr);
58}