blob: 700f500187a78056233e197ed6dc417a85050c49 [file] [log] [blame]
developer451d49d2022-11-16 21:52:21 +08001/*
2 * Copyright (c) 2023, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <common/debug.h>
9#include <drivers/spm/mt_spm_resource_req.h>
10#include <lib/pm/mtk_pm.h>
11#include <lpm/mt_lp_api.h>
12#include <lpm/mt_lp_rm.h>
13#include <mt_spm.h>
14#include <mt_spm_cond.h>
15#include <mt_spm_conservation.h>
16#include <mt_spm_constraint.h>
17#include <mt_spm_idle.h>
18#include <mt_spm_internal.h>
19#include <mt_spm_notifier.h>
20#include "mt_spm_rc_api.h"
21#include "mt_spm_rc_internal.h"
22#include <mt_spm_reg.h>
23#include <mt_spm_suspend.h>
24
25#define CONSTRAINT_SYSPLL_ALLOW (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
26 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
27 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
28 MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
29
30#define CONSTRAINT_SYSPLL_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
31 SPM_FLAG_DISABLE_VCORE_DVS | \
32 SPM_FLAG_DISABLE_VCORE_DFS | \
33 SPM_FLAG_SRAM_SLEEP_CTRL | \
34 SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
35 SPM_FLAG_ENABLE_6315_CTRL | \
36 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
37 SPM_FLAG_USE_SRCCLKENO2)
38
39#define CONSTRAINT_SYSPLL_PCM_FLAG1 (0)
40
41/* If sspm sram won't enter sleep voltage then vcore couldn't enter low power mode */
42#if defined(MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT) && SPM_SRAM_SLEEP_RC_RES_RESTRICT
43#define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
44#else
45#define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
46#endif
47
48static unsigned int syspll_ext_opand2;
49static unsigned short ext_status_syspll;
50
51static struct mt_spm_cond_tables cond_syspll = {
52 .table_cg = {
53 0xFF5DD002, /* MTCMOS1 */
54 0x0000003C, /* MTCMOS2 */
55 0x27AF8000, /* INFRA0 */
56 0x20010876, /* INFRA1 */
57 0x86000640, /* INFRA2 */
58 0x30008020, /* INFRA3 */
59 0x80000000, /* INFRA4 */
60 0x01002A0B, /* PERI0 */
61 0x00090000, /* VPPSYS0_0 */
62 0x38FF3E69, /* VPPSYS0_1 */
63 0xF0081450, /* VPPSYS1_0 */
64 0x00003000, /* VPPSYS1_1 */
65 0x00000000, /* VDOSYS0_0 */
66 0x00000000, /* VDOSYS0_1 */
67 0x000001FF, /* VDOSYS1_0 */
68 0x008001E0, /* VDOSYS1_1 */
69 0x00FB0007, /* VDOSYS1_2 */
70 },
71 .table_pll = 0U,
72};
73
74static struct mt_spm_cond_tables cond_syspll_res = {
75 .table_cg = { 0U },
76 .table_pll = 0U,
77};
78
79static struct constraint_status status = {
80 .id = MT_RM_CONSTRAINT_ID_SYSPLL,
81 .is_valid = (MT_SPM_RC_VALID_SW |
82 MT_SPM_RC_VALID_COND_CHECK |
83 MT_SPM_RC_VALID_COND_LATCH |
84 MT_SPM_RC_VALID_XSOC_BBLPM |
85 MT_SPM_RC_VALID_TRACE_TIME),
86 .is_cond_block = 0U,
87 .enter_cnt = 0U,
88 .cond_res = &cond_syspll_res,
89 .residency = 0ULL,
90};
91
92int spm_syspll_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
93{
94 unsigned int res_req = CONSTRAINT_SYSPLL_RESOURCE_REQ;
95
96 if ((spm_lp == NULL) || (resource_req == NULL)) {
97 return -1;
98 }
99
100 spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
101 spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
102
103 *resource_req |= res_req;
104 return 0;
105}
106
107bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
108{
109 return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK) > 0) &&
110 IS_MT_RM_RC_READY(status.is_valid) &&
111 (IS_PLAT_SUSPEND_ID(state_id) ||
112 (state_id == MT_PLAT_PWR_STATE_SYSTEM_PLL) ||
113 (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
114}
115
116static int update_rc_condition(const void *val)
117{
118 int res = MT_RM_STATUS_OK;
119
120 const struct mt_spm_cond_tables * const tlb =
121 (const struct mt_spm_cond_tables * const)val;
122 const struct mt_spm_cond_tables *tlb_check =
123 (const struct mt_spm_cond_tables *)&cond_syspll;
124
125 if (tlb == NULL) {
126 return MT_RM_STATUS_BAD;
127 }
128
129 status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
130 (status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
131 &cond_syspll_res : NULL);
132 return res;
133}
134
135static void update_rc_clkbuf_status(const void *val)
136{
137 unsigned int is_flight = (val) ? !!(*((unsigned int *)val) == FLIGHT_MODE_ON) : 0;
138
139 if (is_flight != 0U) {
140 spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
141 MT_RM_CONSTRAINT_ID_SYSPLL,
142 MT_SPM_RC_VALID_FLIGHTMODE,
143 (struct constraint_status * const)&status);
144 } else {
145 spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
146 MT_RM_CONSTRAINT_ID_SYSPLL,
147 MT_SPM_RC_VALID_FLIGHTMODE,
148 (struct constraint_status * const)&status);
149 }
150}
151
152static void update_rc_ufs_status(const void *val)
153{
154 unsigned int is_ufs_h8 = (val) ? !!(*((unsigned int *)val) == UFS_REF_CLK_OFF) : 0;
155
156 if (is_ufs_h8 != 0U) {
157 spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
158 MT_RM_CONSTRAINT_ID_SYSPLL,
159 MT_SPM_RC_VALID_UFS_H8,
160 (struct constraint_status * const)&status);
161 } else {
162 spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
163 MT_RM_CONSTRAINT_ID_SYSPLL,
164 MT_SPM_RC_VALID_UFS_H8,
165 (struct constraint_status * const)&status);
166 }
167}
168
169static void update_rc_usb_peri(const void *val)
170{
171 int *flag = (int *)val;
172
173 if (flag == NULL) {
174 return;
175 }
176
177 if (*flag != 0) {
178 SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
179 } else {
180 SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
181 }
182}
183
184static void update_rc_usb_infra(const void *val)
185{
186 int *flag = (int *)val;
187
188 if (flag == NULL) {
189 return;
190 }
191
192 if (*flag != 0) {
193 SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
194 } else {
195 SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
196 }
197}
198
199static void update_rc_status(const void *val)
200{
201 const struct rc_common_state *st;
202
203 st = (const struct rc_common_state *)val;
204
205 if (st == NULL) {
206 return;
207 }
208
209 if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
210 struct mt_spm_cond_tables * const tlb = &cond_syspll;
211
212 spm_rc_condition_modifier(st->id, st->act, st->value,
213 MT_RM_CONSTRAINT_ID_SYSPLL, tlb);
214 } else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
215 (st->type == CONSTRAINT_RESIDNECY)) {
216 spm_rc_constraint_status_set(st->id, st->type, st->act,
217 MT_RM_CONSTRAINT_ID_SYSPLL,
218 (struct constraint_status * const)st->value,
219 (struct constraint_status * const)&status);
220 } else {
221 INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
222 }
223}
224
225int spm_update_rc_syspll(int state_id, int type, const void *val)
226{
227 int res = MT_RM_STATUS_OK;
228
229 switch (type) {
230 case PLAT_RC_UPDATE_CONDITION:
231 res = update_rc_condition(val);
232 break;
233 case PLAT_RC_CLKBUF_STATUS:
234 update_rc_clkbuf_status(val);
235 break;
236 case PLAT_RC_UFS_STATUS:
237 update_rc_ufs_status(val);
238 break;
239 case PLAT_RC_IS_USB_PERI:
240 update_rc_usb_peri(val);
241 break;
242 case PLAT_RC_IS_USB_INFRA:
243 update_rc_usb_infra(val);
244 break;
245 case PLAT_RC_STATUS:
246 update_rc_status(val);
247 break;
248 default:
249 INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
250 break;
251 }
252 return res;
253}
254
255unsigned int spm_allow_rc_syspll(int state_id)
256{
257 return CONSTRAINT_SYSPLL_ALLOW;
258}
259
260int spm_run_rc_syspll(unsigned int cpu, int state_id)
261{
262 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
263 unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
264
265 ext_status_syspll = status.is_valid;
266
267 if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
268#ifdef MT_SPM_USING_SRCLKEN_RC
269 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
270#else
271 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
272#endif
273 }
274
275#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
276 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
277 MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0));
278#else
279 (void)allows;
280#endif
281 if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
282 ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
283 }
284
285 if (IS_PLAT_SUSPEND_ID(state_id)) {
286 mt_spm_suspend_enter(state_id,
287 (syspll_ext_opand2 | MT_SPM_EX_OP_CLR_26M_RECORD |
288 MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT |
289 MT_SPM_EX_OP_SET_SUSPEND_MODE),
290 CONSTRAINT_SYSPLL_RESOURCE_REQ);
291 } else {
292 mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
293 }
294
295 return 0;
296}
297
298int spm_reset_rc_syspll(unsigned int cpu, int state_id)
299{
300 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
301 unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
302
303 if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
304#ifdef MT_SPM_USING_SRCLKEN_RC
305 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
306#else
307 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
308#endif
309 }
310
311#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
312 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
313#else
314 (void)allows;
315#endif
316 if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
317 ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
318 }
319
320 if (IS_PLAT_SUSPEND_ID(state_id)) {
321 mt_spm_suspend_resume(state_id,
322 (syspll_ext_opand2 | MT_SPM_EX_OP_SET_SUSPEND_MODE |
323 MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
324 NULL);
325 } else {
326 struct wake_status *waken = NULL;
327
328 if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
329 ext_op |= MT_SPM_EX_OP_TRACE_LP;
330 }
331
332 mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
333 status.enter_cnt++;
334
335 if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
336 status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
337 }
338 }
339
340 return 0;
341}
342
343int spm_get_status_rc_syspll(unsigned int type, void *priv)
344{
345 int ret = MT_RM_STATUS_OK;
346
347 if (type == PLAT_RC_STATUS) {
348 int res = 0;
349 struct rc_common_state *st = (struct rc_common_state *)priv;
350
351 if (st == NULL) {
352 return MT_RM_STATUS_BAD;
353 }
354
355 res = spm_rc_constraint_status_get(st->id, st->type, st->act,
356 MT_RM_CONSTRAINT_ID_SYSPLL,
357 (struct constraint_status * const)&status,
358 (struct constraint_status * const)st->value);
359 if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
360 ret = MT_RM_STATUS_STOP;
361 }
362 }
363 return ret;
364}