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git01.mediatek.com / filogic / atf / 1f55c4110e1008cafc05497a81b0b4443a854417 / . / plat / arm / board / rdn2 / include / platform_def.h
blob: 8e63de5808b28a15ddc023673acb660627c33f32 [file] [log] [blame]
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]1/*
Tony K Nadackala81a3d92021-11-24 16:09:26 +0000[diff] [blame]2 * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved.
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
10#include <lib/utils_def.h>
11
12#include <sgi_soc_platform_def_v2.h>
13
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]14#if (CSS_SGI_PLATFORM_VARIANT == 1)
15#define PLAT_ARM_CLUSTER_COUNT U(8)
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]16#elif (CSS_SGI_PLATFORM_VARIANT == 2)
17#define PLAT_ARM_CLUSTER_COUNT U(4)
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]18#else
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]19#define PLAT_ARM_CLUSTER_COUNT U(16)
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]20#endif
21
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]22#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
23#define CSS_SGI_MAX_PE_PER_CPU U(1)
24
25#define PLAT_CSS_MHU_BASE UL(0x2A920000)
26#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
27
28#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
29#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
30
31/* TZC Related Constants */
Vijayenthiran Subramaniam478ccb32021-02-04 18:15:40 +0530[diff] [blame]32#define PLAT_ARM_TZC_BASE UL(0x10720000)
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]33#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
34
35#define TZC400_OFFSET UL(0x1000000)
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]36
37#if (CSS_SGI_PLATFORM_VARIANT == 1)
38#define TZC400_COUNT U(2)
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]39#elif (CSS_SGI_PLATFORM_VARIANT == 2)
40#define TZC400_COUNT U(4)
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]41#else
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]42#define TZC400_COUNT U(8)
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]43#endif
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]44
45#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
46 (n * TZC400_OFFSET))
47
48#define TZC_NSAID_ALL_AP U(0)
49#define TZC_NSAID_PCI U(1)
50#define TZC_NSAID_HDLCD0 U(2)
Vijayenthiran Subramaniam673e0592021-07-06 14:52:04 +0530[diff] [blame]51#define TZC_NSAID_DMA U(5)
52#define TZC_NSAID_DMA2 U(8)
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]53#define TZC_NSAID_CLCD U(7)
54#define TZC_NSAID_AP U(9)
55#define TZC_NSAID_VIRTIO U(15)
56
57#define PLAT_ARM_TZC_NS_DEV_ACCESS \
58 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
59 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
60 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
Vijayenthiran Subramaniam673e0592021-07-06 14:52:04 +0530[diff] [blame]61 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA)) | \
62 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA2)) | \
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]63 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
64 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
65 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
66
67/*
68 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
69 */
70#ifdef __aarch64__
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]71#if (CSS_SGI_PLATFORM_VARIANT == 2)
Vijayenthiran Subramaniam00cd0802022-01-25 20:37:20 +0530[diff] [blame]72#define CSS_SGI_ADDR_BITS_PER_CHIP U(46) /* 64TB */
73#else
74#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) /* 4TB */
75#endif
76
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]77#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
78 CSS_SGI_CHIP_COUNT)
79#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
80 CSS_SGI_CHIP_COUNT)
81#else
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]82#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
83#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
84#endif
85
86/* GIC related constants */
87#define PLAT_ARM_GICD_BASE UL(0x30000000)
88#define PLAT_ARM_GICC_BASE UL(0x2C000000)
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]89
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]90/* Virtual address used by dynamic mem_protect for chunk_base */
91#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
92
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]93#if (CSS_SGI_PLATFORM_VARIANT == 1)
94#define PLAT_ARM_GICR_BASE UL(0x30100000)
Tony K Nadackala81a3d92021-11-24 16:09:26 +0000[diff] [blame]95#elif (CSS_SGI_PLATFORM_VARIANT == 3)
96#define PLAT_ARM_GICR_BASE UL(0x30300000)
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]97#else
Vijayenthiran Subramaniam777a9ff2020-12-15 20:07:43 +0530[diff] [blame]98#define PLAT_ARM_GICR_BASE UL(0x301C0000)
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]99#endif
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]100
Pranav Madhu078dc522022-07-27 14:01:24 +0530[diff] [blame]101/* Interrupt priority level for shutdown/reboot */
102#define PLAT_REBOOT_PRI GIC_HIGHEST_SEC_PRIORITY
103#define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_REBOOT_PRI)
104
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]105#endif /* PLATFORM_DEF_H */