Jun Nie | d85efcf | 2019-06-13 11:47:09 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <arch.h> |
| 11 | #include <common/tbbr/tbbr_img_def.h> |
| 12 | #include <plat/common/common_def.h> |
| 13 | |
| 14 | #define PLATFORM_STACK_SIZE 0x1000 |
| 15 | |
Deepika Bhavnani | 92efb23 | 2019-12-13 10:47:06 -0600 | [diff] [blame] | 16 | #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) |
| 17 | #define PLATFORM_CLUSTER_COUNT U(1) |
Jun Nie | d85efcf | 2019-06-13 11:47:09 +0800 | [diff] [blame] | 18 | #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER |
| 19 | |
| 20 | #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT |
| 21 | |
Deepika Bhavnani | 92efb23 | 2019-12-13 10:47:06 -0600 | [diff] [blame] | 22 | #define PICOPI_PRIMARY_CPU U(0) |
Jun Nie | d85efcf | 2019-06-13 11:47:09 +0800 | [diff] [blame] | 23 | |
Deepika Bhavnani | 92efb23 | 2019-12-13 10:47:06 -0600 | [diff] [blame] | 24 | #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ |
Jun Nie | d85efcf | 2019-06-13 11:47:09 +0800 | [diff] [blame] | 25 | PLATFORM_CORE_COUNT) |
| 26 | #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 |
| 27 | |
| 28 | #define PLAT_MAX_RET_STATE 1 |
| 29 | #define PLAT_MAX_OFF_STATE 2 |
| 30 | |
| 31 | /* Local power state for power domains in Run state. */ |
| 32 | #define PLAT_LOCAL_STATE_RUN 0 |
| 33 | |
| 34 | /* Local power state for retention. Valid only for CPU power domains */ |
| 35 | #define PLAT_LOCAL_STATE_RET 1 |
| 36 | |
| 37 | /* |
| 38 | * Local power state for OFF/power-down. Valid for CPU and cluster power |
| 39 | * domains. |
| 40 | */ |
| 41 | #define PLAT_LOCAL_STATE_OFF 2 |
| 42 | |
| 43 | /* |
| 44 | * Macros used to parse state information from State-ID if it is using the |
| 45 | * recommended encoding for State-ID. |
| 46 | */ |
| 47 | #define PLAT_LOCAL_PSTATE_WIDTH 4 |
| 48 | #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) |
| 49 | |
| 50 | /* |
| 51 | * Some data must be aligned on the biggest cache line size in the platform. |
| 52 | * This is known only to the platform as it might have a combination of |
| 53 | * integrated and external caches. |
| 54 | * i.MX7 has a 32 byte cacheline size |
| 55 | * i.MX 7Dual Applications Processor Reference Manual, Rev. 1, 01/2018 pg 298 |
| 56 | */ |
| 57 | #define CACHE_WRITEBACK_SHIFT 4 |
| 58 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 59 | |
| 60 | /* |
| 61 | * Partition memory into secure BootROM, OCRAM_S, non-secure DRAM, secure DRAM |
| 62 | */ |
| 63 | #define BOOT_ROM_BASE 0x00000000 |
| 64 | #define BOOT_ROM_SIZE 0x00020000 |
| 65 | |
| 66 | #define OCRAM_S_BASE 0x00180000 |
| 67 | #define OCRAM_S_SIZE 0x00008000 |
| 68 | |
| 69 | /* Controller maps 2GB, board contains 512 MB. 0x80000000 - 0xa0000000 */ |
| 70 | #define DRAM_BASE 0x80000000 |
| 71 | #define DRAM_SIZE 0x20000000 |
| 72 | #define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE) |
| 73 | |
| 74 | /* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */ |
| 75 | #define IMX7_OPTEE_SIZE 0x02000000 |
| 76 | #define IMX7_OPTEE_BASE (DRAM_LIMIT - IMX7_OPTEE_SIZE) |
| 77 | #define IMX7_OPTEE_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE) |
| 78 | |
| 79 | /* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */ |
| 80 | #define BL2_RAM_SIZE 0x00100000 |
| 81 | #define BL2_RAM_BASE (IMX7_OPTEE_BASE - BL2_RAM_SIZE) |
| 82 | #define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE) |
| 83 | |
| 84 | /* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/ |
| 85 | #define SHARED_RAM_SIZE 0x00001000 |
| 86 | #define SHARED_RAM_BASE (BL2_RAM_BASE - SHARED_RAM_SIZE) |
| 87 | #define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE) |
| 88 | |
| 89 | /* Define the absolute location of u-boot 0x87800000 - 0x87900000 */ |
| 90 | #define IMX7_UBOOT_SIZE 0x00100000 |
| 91 | #define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000) |
| 92 | #define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE) |
| 93 | |
| 94 | /* Define FIP image absolute location 0x80000000 - 0x80100000 */ |
Ying-Chun Liu (PaulLiu) | 54cabc4 | 2021-04-07 06:10:32 +0800 | [diff] [blame] | 95 | #define IMX_FIP_SIZE 0x00100000 |
| 96 | #define IMX_FIP_BASE (DRAM_BASE) |
| 97 | #define IMX_FIP_LIMIT (IMX_FIP_BASE + IMX_FIP_SIZE) |
Jun Nie | d85efcf | 2019-06-13 11:47:09 +0800 | [diff] [blame] | 98 | |
| 99 | /* Define FIP image location at 1MB offset */ |
Ying-Chun Liu (PaulLiu) | 54cabc4 | 2021-04-07 06:10:32 +0800 | [diff] [blame] | 100 | #define IMX_FIP_MMC_BASE (1024 * 1024) |
Jun Nie | d85efcf | 2019-06-13 11:47:09 +0800 | [diff] [blame] | 101 | |
| 102 | /* Define the absolute location of DTB 0x83000000 - 0x83100000 */ |
| 103 | #define IMX7_DTB_SIZE 0x00100000 |
| 104 | #define IMX7_DTB_BASE (DRAM_BASE + 0x03000000) |
| 105 | #define IMX7_DTB_LIMIT (IMX7_DTB_BASE + IMX7_DTB_SIZE) |
| 106 | |
| 107 | /* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */ |
| 108 | #define IMX7_DTB_OVERLAY_SIZE 0x00001000 |
| 109 | #define IMX7_DTB_OVERLAY_BASE IMX7_DTB_LIMIT |
| 110 | #define IMX7_DTB_OVERLAY_LIMIT (IMX7_DTB_OVERLAY_BASE + \ |
| 111 | IMX7_DTB_OVERLAY_SIZE) |
| 112 | /* |
| 113 | * BL2 specific defines. |
| 114 | * |
| 115 | * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug |
| 116 | * size plus a little space for growth. |
| 117 | */ |
| 118 | #define BL2_BASE BL2_RAM_BASE |
| 119 | #define BL2_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE) |
| 120 | |
| 121 | /* |
| 122 | * BL3-2/OPTEE |
| 123 | */ |
| 124 | # define BL32_BASE IMX7_OPTEE_BASE |
| 125 | # define BL32_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE) |
| 126 | |
| 127 | /* |
| 128 | * BL3-3/U-BOOT |
| 129 | */ |
| 130 | #define BL33_BASE IMX7_UBOOT_BASE |
| 131 | #define BL33_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE) |
| 132 | |
| 133 | /* |
| 134 | * ATF's view of memory |
| 135 | * |
| 136 | * 0xa0000000 +-----------------+ |
| 137 | * | DDR | BL32/OPTEE |
| 138 | * 0x9e000000 +-----------------+ |
| 139 | * | DDR | BL23 ATF |
| 140 | * 0x9df00000 +-----------------+ |
| 141 | * | DDR | Shared MBOX RAM |
| 142 | * 0x9de00000 +-----------------+ |
| 143 | * | DDR | Unallocated |
| 144 | * 0x87900000 +-----------------+ |
| 145 | * | DDR | BL33/U-BOOT |
| 146 | * 0x87800000 +-----------------+ |
| 147 | * | DDR | Unallocated |
| 148 | * 0x83100000 +-----------------+ |
| 149 | * | DDR | DTB |
| 150 | * 0x83000000 +-----------------+ |
| 151 | * | DDR | Unallocated |
| 152 | * 0x80100000 +-----------------+ |
| 153 | * | DDR | FIP |
| 154 | * 0x80000000 +-----------------+ |
| 155 | * | SOC I/0 | |
| 156 | * 0x00a00000 +-----------------+ |
| 157 | * | OCRAM | Not used |
| 158 | * 0x00900000 +-----------------+ |
| 159 | * | SOC I/0 | |
| 160 | * 0x00188000 +-----------------+ |
| 161 | * | OCRAM_S | Not used |
| 162 | * 0x00180000 +-----------------+ |
| 163 | * | SOC I/0 | |
| 164 | * 0x00020000 +-----------------+ |
| 165 | * | BootROM | BL1 |
| 166 | * 0x00000000 +-----------------+ |
| 167 | */ |
| 168 | |
| 169 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 170 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 171 | #define MAX_MMAP_REGIONS 10 |
| 172 | #define MAX_XLAT_TABLES 6 |
| 173 | #define MAX_IO_DEVICES 2 |
| 174 | #define MAX_IO_HANDLES 3 |
| 175 | #define MAX_IO_BLOCK_DEVICES 1 |
| 176 | |
| 177 | /* UART defines */ |
| 178 | #define PLAT_IMX7_BOOT_UART_BASE MXC_UART5_BASE |
| 179 | #define PLAT_IMX7_BOOT_UART_CLK_IN_HZ 24000000 |
| 180 | #define PLAT_IMX7_CONSOLE_BAUDRATE 115200 |
| 181 | |
| 182 | /* MMC defines */ |
| 183 | #ifndef PLAT_PICOPI_SD |
| 184 | #define PLAT_PICOPI_SD 3 |
| 185 | #endif |
| 186 | |
| 187 | #if PLAT_PICOPI_SD == 1 |
| 188 | #define PLAT_PICOPI_BOOT_MMC_BASE USDHC1_BASE |
| 189 | #endif /* PLAT_PICOPI_SD == 1 */ |
| 190 | |
| 191 | #if PLAT_PICOPI_SD == 2 |
| 192 | #define PLAT_PICOPI_BOOT_MMC_BASE USDHC2_BASE |
| 193 | #endif /* PLAT_PICOPI_SD == 2 */ |
| 194 | |
| 195 | #if PLAT_PICOPI_SD == 3 |
| 196 | #define PLAT_PICOPI_BOOT_MMC_BASE USDHC3_BASE |
| 197 | #endif /* PLAT_PICOPI_SD == 3 */ |
| 198 | |
| 199 | /* |
| 200 | * System counter |
| 201 | */ |
| 202 | #define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */ |
| 203 | |
| 204 | #endif /* PLATFORM_DEF_H */ |