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Antonio Nino Diaz272e8712018-09-18 01:36:00 +01001/*
Carlo Caione189494a2019-08-23 18:28:36 +01002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz272e8712018-09-18 01:36:00 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
Antonio Nino Diaz272e8712018-09-18 01:36:00 +01008#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <platform_def.h>
11
12#include <bl31/interrupt_mgmt.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
15#include <common/ep_info.h>
Carlo Caione189494a2019-08-23 18:28:36 +010016#include <drivers/amlogic/meson_console.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <lib/mmio.h>
18#include <lib/xlat_tables/xlat_tables_v2.h>
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010019
20/*******************************************************************************
21 * Platform memory map regions
22 ******************************************************************************/
Carlo Caione1e3e33b2019-08-28 15:32:22 +010023#define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
24 AML_NSDRAM0_SIZE, \
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010025 MT_MEMORY | MT_RW | MT_NS)
26
Carlo Caione1e3e33b2019-08-28 15:32:22 +010027#define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
28 AML_NSDRAM1_SIZE, \
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010029 MT_MEMORY | MT_RW | MT_NS)
30
Carlo Caione1e3e33b2019-08-28 15:32:22 +010031#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
32 AML_SEC_DEVICE0_SIZE, \
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010033 MT_DEVICE | MT_RW | MT_SECURE)
34
Carlo Caione1e3e33b2019-08-28 15:32:22 +010035#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
36 AML_SEC_DEVICE1_SIZE, \
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010037 MT_DEVICE | MT_RW | MT_SECURE)
38
Carlo Caione1e3e33b2019-08-28 15:32:22 +010039#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
40 AML_TZRAM_SIZE, \
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010041 MT_DEVICE | MT_RW | MT_SECURE)
42
Carlo Caione1e3e33b2019-08-28 15:32:22 +010043#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
44 AML_SEC_DEVICE2_SIZE, \
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010045 MT_DEVICE | MT_RW | MT_SECURE)
46
Carlo Caione1e3e33b2019-08-28 15:32:22 +010047#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
48 AML_SEC_DEVICE3_SIZE, \
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010049 MT_DEVICE | MT_RW | MT_SECURE)
50
51static const mmap_region_t gxbb_mmap[] = {
52 MAP_NSDRAM0,
53 MAP_NSDRAM1,
54 MAP_SEC_DEVICE0,
55 MAP_SEC_DEVICE1,
56 MAP_TZRAM,
57 MAP_SEC_DEVICE2,
58 MAP_SEC_DEVICE3,
59 {0}
60};
61
62/*******************************************************************************
63 * Per-image regions
64 ******************************************************************************/
65#define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
66 BL31_END - BL31_BASE, \
67 MT_MEMORY | MT_RW | MT_SECURE)
68
69#define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
70 BL_CODE_END - BL_CODE_BASE, \
71 MT_CODE | MT_SECURE)
72
73#define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
74 BL_RO_DATA_END - BL_RO_DATA_BASE, \
75 MT_RO_DATA | MT_SECURE)
76
77#define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \
78 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
79 MT_DEVICE | MT_RW | MT_SECURE)
80
81/*******************************************************************************
82 * Function that sets up the translation tables.
83 ******************************************************************************/
Carlo Caionebf2d6262019-08-25 18:09:03 +010084void aml_setup_page_tables(void)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010085{
86#if IMAGE_BL31
87 const mmap_region_t gxbb_bl_mmap[] = {
88 MAP_BL31,
89 MAP_BL_CODE,
90 MAP_BL_RO_DATA,
91#if USE_COHERENT_MEM
92 MAP_BL_COHERENT,
93#endif
94 {0}
95 };
96#endif
97
98 mmap_add(gxbb_bl_mmap);
99
100 mmap_add(gxbb_mmap);
101
102 init_xlat_tables();
103}
104
105/*******************************************************************************
106 * Function that sets up the console
107 ******************************************************************************/
108static console_meson_t gxbb_console;
109
Carlo Caionebf2d6262019-08-25 18:09:03 +0100110void aml_console_init(void)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +0100111{
Carlo Caione1afdfb02019-08-24 18:47:06 +0100112 int rc = console_meson_register(AML_UART0_AO_BASE,
113 AML_UART0_AO_CLK_IN_HZ,
114 AML_UART_BAUDRATE,
Antonio Nino Diaz272e8712018-09-18 01:36:00 +0100115 &gxbb_console);
116 if (rc == 0) {
117 /*
118 * The crash console doesn't use the multi console API, it uses
119 * the core console functions directly. It is safe to call panic
120 * and let it print debug information.
121 */
122 panic();
123 }
124
125 console_set_scope(&gxbb_console.console,
126 CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
127}
128
129/*******************************************************************************
130 * Function that returns the system counter frequency
131 ******************************************************************************/
132unsigned int plat_get_syscnt_freq2(void)
133{
134 uint32_t val;
135
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100136 val = mmio_read_32(AML_SYS_CPU_CFG7);
Antonio Nino Diaz272e8712018-09-18 01:36:00 +0100137 val &= 0xFDFFFFFF;
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100138 mmio_write_32(AML_SYS_CPU_CFG7, val);
Antonio Nino Diaz272e8712018-09-18 01:36:00 +0100139
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100140 val = mmio_read_32(AML_AO_TIMESTAMP_CNTL);
Antonio Nino Diaz272e8712018-09-18 01:36:00 +0100141 val &= 0xFFFFFE00;
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100142 mmio_write_32(AML_AO_TIMESTAMP_CNTL, val);
Antonio Nino Diaz272e8712018-09-18 01:36:00 +0100143
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100144 return AML_OSC24M_CLK_IN_HZ;
Antonio Nino Diaz272e8712018-09-18 01:36:00 +0100145}