Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 31 | #include <arch_helpers.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 32 | #include <assert.h> |
| 33 | #include <debug.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 34 | #include <memctrl.h> |
Varun Wadekar | 7a9a285 | 2015-09-18 11:21:22 +0530 | [diff] [blame] | 35 | #include <memctrl_v1.h> |
| 36 | #include <mmio.h> |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 37 | #include <string.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 38 | #include <tegra_def.h> |
Douglas Raillard | a8954fc | 2017-01-26 15:54:44 +0000 | [diff] [blame] | 39 | #include <utils.h> |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 40 | #include <xlat_tables.h> |
| 41 | |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 42 | #define TEGRA_GPU_RESET_REG_OFFSET 0x28c |
| 43 | #define GPU_RESET_BIT (1 << 24) |
| 44 | |
| 45 | /* Video Memory base and size (live values) */ |
| 46 | static uintptr_t video_mem_base; |
| 47 | static uint64_t video_mem_size; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 48 | |
| 49 | /* |
| 50 | * Init SMMU. |
| 51 | */ |
| 52 | void tegra_memctrl_setup(void) |
| 53 | { |
| 54 | /* |
| 55 | * Setup the Memory controller to allow only secure accesses to |
| 56 | * the TZDRAM carveout |
| 57 | */ |
Varun Wadekar | 7a9a285 | 2015-09-18 11:21:22 +0530 | [diff] [blame] | 58 | INFO("Tegra Memory Controller (v1)\n"); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 59 | |
| 60 | /* allow translations for all MC engines */ |
| 61 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0, |
| 62 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 63 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_1_0, |
| 64 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 65 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_2_0, |
| 66 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 67 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_3_0, |
| 68 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 69 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_4_0, |
| 70 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 71 | |
| 72 | tegra_mc_write_32(MC_SMMU_ASID_SECURITY_0, MC_SMMU_ASID_SECURITY); |
| 73 | |
| 74 | tegra_mc_write_32(MC_SMMU_TLB_CONFIG_0, MC_SMMU_TLB_CONFIG_0_RESET_VAL); |
| 75 | tegra_mc_write_32(MC_SMMU_PTC_CONFIG_0, MC_SMMU_PTC_CONFIG_0_RESET_VAL); |
| 76 | |
| 77 | /* flush PTC and TLB */ |
| 78 | tegra_mc_write_32(MC_SMMU_PTC_FLUSH_0, MC_SMMU_PTC_FLUSH_ALL); |
| 79 | (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ |
| 80 | tegra_mc_write_32(MC_SMMU_TLB_FLUSH_0, MC_SMMU_TLB_FLUSH_ALL); |
| 81 | |
| 82 | /* enable SMMU */ |
| 83 | tegra_mc_write_32(MC_SMMU_CONFIG_0, |
| 84 | MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE); |
| 85 | (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 86 | |
| 87 | /* video memory carveout */ |
| 88 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, video_mem_base); |
| 89 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | /* |
| 93 | * Secure the BL31 DRAM aperture. |
| 94 | * |
| 95 | * phys_base = physical base of TZDRAM aperture |
| 96 | * size_in_bytes = size of aperture in bytes |
| 97 | */ |
| 98 | void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 99 | { |
| 100 | /* |
| 101 | * Setup the Memory controller to allow only secure accesses to |
| 102 | * the TZDRAM carveout |
| 103 | */ |
| 104 | INFO("Configuring TrustZone DRAM Memory Carveout\n"); |
| 105 | |
| 106 | tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base); |
| 107 | tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); |
| 108 | } |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 109 | |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 110 | static void tegra_clear_videomem(uintptr_t non_overlap_area_start, |
| 111 | unsigned long long non_overlap_area_size) |
| 112 | { |
| 113 | /* |
| 114 | * Perform cache maintenance to ensure that the non-overlapping area is |
| 115 | * zeroed out. The first invalidation of this range ensures that |
| 116 | * possible evictions of dirty cache lines do not interfere with the |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 117 | * 'zeromem' operation. Other CPUs could speculatively prefetch the |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 118 | * main memory contents of this area between the first invalidation and |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 119 | * the 'zeromem' operation. The second invalidation ensures that any |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 120 | * such cache lines are removed as well. |
| 121 | */ |
| 122 | inv_dcache_range(non_overlap_area_start, non_overlap_area_size); |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 123 | zeromem((void *)non_overlap_area_start, non_overlap_area_size); |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 124 | inv_dcache_range(non_overlap_area_start, non_overlap_area_size); |
| 125 | } |
| 126 | |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 127 | /* |
| 128 | * Program the Video Memory carveout region |
| 129 | * |
| 130 | * phys_base = physical base of aperture |
| 131 | * size_in_bytes = size of aperture in bytes |
| 132 | */ |
| 133 | void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 134 | { |
| 135 | uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20); |
| 136 | uintptr_t vmem_end_new = phys_base + size_in_bytes; |
| 137 | uint32_t regval; |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 138 | unsigned long long non_overlap_area_size; |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 139 | |
| 140 | /* |
| 141 | * The GPU is the user of the Video Memory region. In order to |
| 142 | * transition to the new memory region smoothly, we program the |
| 143 | * new base/size ONLY if the GPU is in reset mode. |
| 144 | */ |
| 145 | regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); |
| 146 | if ((regval & GPU_RESET_BIT) == 0) { |
| 147 | ERROR("GPU not in reset! Video Memory setup failed\n"); |
| 148 | return; |
| 149 | } |
| 150 | |
| 151 | /* |
| 152 | * Setup the Memory controller to restrict CPU accesses to the Video |
| 153 | * Memory region |
| 154 | */ |
| 155 | INFO("Configuring Video Memory Carveout\n"); |
| 156 | |
| 157 | /* |
| 158 | * Configure Memory Controller directly for the first time. |
| 159 | */ |
| 160 | if (video_mem_base == 0) |
| 161 | goto done; |
| 162 | |
| 163 | /* |
| 164 | * Clear the old regions now being exposed. The following cases |
| 165 | * can occur - |
| 166 | * |
| 167 | * 1. clear whole old region (no overlap with new region) |
| 168 | * 2. clear old sub-region below new base |
| 169 | * 3. clear old sub-region above new end |
| 170 | */ |
| 171 | INFO("Cleaning previous Video Memory Carveout\n"); |
| 172 | |
| 173 | disable_mmu_el3(); |
Varun Wadekar | 1be2f97 | 2015-08-26 15:06:14 +0530 | [diff] [blame] | 174 | if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) { |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 175 | tegra_clear_videomem(video_mem_base, video_mem_size << 20); |
Varun Wadekar | 1be2f97 | 2015-08-26 15:06:14 +0530 | [diff] [blame] | 176 | } else { |
| 177 | if (video_mem_base < phys_base) { |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 178 | non_overlap_area_size = phys_base - video_mem_base; |
| 179 | tegra_clear_videomem(video_mem_base, non_overlap_area_size); |
Varun Wadekar | 1be2f97 | 2015-08-26 15:06:14 +0530 | [diff] [blame] | 180 | } |
| 181 | if (vmem_end_old > vmem_end_new) { |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 182 | non_overlap_area_size = vmem_end_old - vmem_end_new; |
| 183 | tegra_clear_videomem(vmem_end_new, non_overlap_area_size); |
Varun Wadekar | 1be2f97 | 2015-08-26 15:06:14 +0530 | [diff] [blame] | 184 | } |
| 185 | } |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 186 | enable_mmu_el3(0); |
| 187 | |
| 188 | done: |
| 189 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, phys_base); |
| 190 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); |
| 191 | |
| 192 | /* store new values */ |
| 193 | video_mem_base = phys_base; |
| 194 | video_mem_size = size_in_bytes >> 20; |
| 195 | } |