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Soby Mathewc6820d12016-05-09 17:49:55 +01001/*
Masahiro Yamada019b4f82020-04-02 15:35:19 +09002 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
Soby Mathewc6820d12016-05-09 17:49:55 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewc6820d12016-05-09 17:49:55 +01005 */
6
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00007#ifndef ARCH_HELPERS_H
8#define ARCH_HELPERS_H
Soby Mathewc6820d12016-05-09 17:49:55 +01009
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010010#include <cdefs.h>
Masahiro Yamada019b4f82020-04-02 15:35:19 +090011#include <stdbool.h>
Soby Mathewc6820d12016-05-09 17:49:55 +010012#include <stdint.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010013#include <string.h>
Soby Mathewc6820d12016-05-09 17:49:55 +010014
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <arch.h>
16
Soby Mathewc6820d12016-05-09 17:49:55 +010017/**********************************************************************
18 * Macros which create inline functions to read or write CPU system
19 * registers
20 *********************************************************************/
21
22#define _DEFINE_COPROCR_WRITE_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
23static inline void write_## _name(u_register_t v) \
24{ \
25 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
26}
27
28#define _DEFINE_COPROCR_READ_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
29static inline u_register_t read_ ## _name(void) \
30{ \
31 u_register_t v; \
32 __asm__ volatile ("mrc "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : "=r" (v));\
33 return v; \
34}
35
36/*
37 * The undocumented %Q and %R extended asm are used to implemented the below
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000038 * 64 bit `mrrc` and `mcrr` instructions.
Soby Mathewc6820d12016-05-09 17:49:55 +010039 */
Soby Mathewc6820d12016-05-09 17:49:55 +010040
41#define _DEFINE_COPROCR_WRITE_FUNC_64(_name, coproc, opc1, CRm) \
42static inline void write64_## _name(uint64_t v) \
43{ \
44 __asm__ volatile ("mcrr "#coproc","#opc1", %Q0, %R0,"#CRm : : "r" (v));\
45}
46
47#define _DEFINE_COPROCR_READ_FUNC_64(_name, coproc, opc1, CRm) \
48static inline uint64_t read64_## _name(void) \
49{ uint64_t v; \
50 __asm__ volatile ("mrrc "#coproc","#opc1", %Q0, %R0,"#CRm : "=r" (v));\
51 return v; \
52}
53
54#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
55static inline u_register_t read_ ## _name(void) \
56{ \
57 u_register_t v; \
58 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
59 return v; \
60}
61
62#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
63static inline void write_ ## _name(u_register_t v) \
64{ \
65 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
66}
67
68#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \
69static inline void write_ ## _name(const u_register_t v) \
70{ \
71 __asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \
72}
73
74/* Define read function for coproc register */
75#define DEFINE_COPROCR_READ_FUNC(_name, ...) \
76 _DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__)
77
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000078/* Define write function for coproc register */
79#define DEFINE_COPROCR_WRITE_FUNC(_name, ...) \
80 _DEFINE_COPROCR_WRITE_FUNC(_name, __VA_ARGS__)
81
Soby Mathewc6820d12016-05-09 17:49:55 +010082/* Define read & write function for coproc register */
83#define DEFINE_COPROCR_RW_FUNCS(_name, ...) \
84 _DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__) \
85 _DEFINE_COPROCR_WRITE_FUNC(_name, __VA_ARGS__)
86
87/* Define 64 bit read function for coproc register */
88#define DEFINE_COPROCR_READ_FUNC_64(_name, ...) \
89 _DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__)
90
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000091/* Define 64 bit write function for coproc register */
92#define DEFINE_COPROCR_WRITE_FUNC_64(_name, ...) \
93 _DEFINE_COPROCR_WRITE_FUNC_64(_name, __VA_ARGS__)
94
Soby Mathewc6820d12016-05-09 17:49:55 +010095/* Define 64 bit read & write function for coproc register */
96#define DEFINE_COPROCR_RW_FUNCS_64(_name, ...) \
97 _DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__) \
98 _DEFINE_COPROCR_WRITE_FUNC_64(_name, __VA_ARGS__)
99
100/* Define read & write function for system register */
101#define DEFINE_SYSREG_RW_FUNCS(_name) \
102 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
103 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
104
105/**********************************************************************
106 * Macros to create inline functions for tlbi operations
107 *********************************************************************/
108
109#define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
110static inline void tlbi##_op(void) \
111{ \
112 u_register_t v = 0; \
113 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
114}
115
Antonio Nino Diazab37d152018-11-22 15:38:05 +0000116#define _DEFINE_BPIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
117static inline void bpi##_op(void) \
Antonio Nino Diazac998032017-02-27 17:23:54 +0000118{ \
119 u_register_t v = 0; \
120 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
121}
122
Soby Mathewc6820d12016-05-09 17:49:55 +0100123#define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
124static inline void tlbi##_op(u_register_t v) \
125{ \
126 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
127}
128
129/* Define function for simple TLBI operation */
130#define DEFINE_TLBIOP_FUNC(_op, ...) \
131 _DEFINE_TLBIOP_FUNC(_op, __VA_ARGS__)
132
133/* Define function for TLBI operation with register parameter */
134#define DEFINE_TLBIOP_PARAM_FUNC(_op, ...) \
135 _DEFINE_TLBIOP_PARAM_FUNC(_op, __VA_ARGS__)
136
Antonio Nino Diazac998032017-02-27 17:23:54 +0000137/* Define function for simple BPI operation */
138#define DEFINE_BPIOP_FUNC(_op, ...) \
139 _DEFINE_BPIOP_FUNC(_op, __VA_ARGS__)
140
Soby Mathewc6820d12016-05-09 17:49:55 +0100141/**********************************************************************
142 * Macros to create inline functions for DC operations
143 *********************************************************************/
144#define _DEFINE_DCOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
145static inline void dc##_op(u_register_t v) \
146{ \
147 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
148}
149
150/* Define function for DC operation with register parameter */
151#define DEFINE_DCOP_PARAM_FUNC(_op, ...) \
152 _DEFINE_DCOP_PARAM_FUNC(_op, __VA_ARGS__)
153
154/**********************************************************************
155 * Macros to create inline functions for system instructions
156 *********************************************************************/
157 /* Define function for simple system instruction */
158#define DEFINE_SYSOP_FUNC(_op) \
159static inline void _op(void) \
160{ \
161 __asm__ (#_op); \
162}
163
164
165/* Define function for system instruction with type specifier */
166#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
167static inline void _op ## _type(void) \
168{ \
Andre Przywara5c29cba2020-10-16 18:19:03 +0100169 __asm__ (#_op " " #_type : : : "memory"); \
Soby Mathewc6820d12016-05-09 17:49:55 +0100170}
171
172/* Define function for system instruction with register parameter */
173#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
174static inline void _op ## _type(u_register_t v) \
175{ \
176 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
177}
178
179void flush_dcache_range(uintptr_t addr, size_t size);
180void clean_dcache_range(uintptr_t addr, size_t size);
181void inv_dcache_range(uintptr_t addr, size_t size);
Masahiro Yamada019b4f82020-04-02 15:35:19 +0900182bool is_dcache_enabled(void);
Soby Mathewc6820d12016-05-09 17:49:55 +0100183
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000184void dcsw_op_louis(u_register_t op_type);
185void dcsw_op_all(u_register_t op_type);
186
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100187void disable_mmu_secure(void);
188void disable_mmu_icache_secure(void);
189
Soby Mathewc6820d12016-05-09 17:49:55 +0100190DEFINE_SYSOP_FUNC(wfi)
191DEFINE_SYSOP_FUNC(wfe)
192DEFINE_SYSOP_FUNC(sev)
193DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
194DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000195DEFINE_SYSOP_TYPE_FUNC(dmb, st)
Jeenu Viswambharan1aa2db32018-09-05 14:23:27 +0100196
197/* dmb ld is not valid for armv7/thumb machines */
198#if ARM_ARCH_MAJOR != 7
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000199DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
Jeenu Viswambharan1aa2db32018-09-05 14:23:27 +0100200#endif
201
Soby Mathewc6820d12016-05-09 17:49:55 +0100202DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000203DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
Soby Mathewc6820d12016-05-09 17:49:55 +0100204DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100205DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
Soby Mathewc6820d12016-05-09 17:49:55 +0100206DEFINE_SYSOP_FUNC(isb)
207
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100208void __dead2 smc(uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3,
209 uint32_t r4, uint32_t r5, uint32_t r6, uint32_t r7);
210
Soby Mathewc6820d12016-05-09 17:49:55 +0100211DEFINE_SYSREG_RW_FUNCS(spsr)
212DEFINE_SYSREG_RW_FUNCS(cpsr)
213
214/*******************************************************************************
215 * System register accessor prototypes
216 ******************************************************************************/
217DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR)
218DEFINE_COPROCR_READ_FUNC(midr, MIDR)
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000219DEFINE_COPROCR_READ_FUNC(id_mmfr4, ID_MMFR4)
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100220DEFINE_COPROCR_READ_FUNC(id_pfr0, ID_PFR0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100221DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1)
222DEFINE_COPROCR_READ_FUNC(isr, ISR)
223DEFINE_COPROCR_READ_FUNC(clidr, CLIDR)
224DEFINE_COPROCR_READ_FUNC_64(cntpct, CNTPCT_64)
225
226DEFINE_COPROCR_RW_FUNCS(scr, SCR)
227DEFINE_COPROCR_RW_FUNCS(ctr, CTR)
228DEFINE_COPROCR_RW_FUNCS(sctlr, SCTLR)
Etienne Carriere70a004b2017-11-05 22:56:03 +0100229DEFINE_COPROCR_RW_FUNCS(actlr, ACTLR)
Soby Mathewc6820d12016-05-09 17:49:55 +0100230DEFINE_COPROCR_RW_FUNCS(hsctlr, HSCTLR)
231DEFINE_COPROCR_RW_FUNCS(hcr, HCR)
232DEFINE_COPROCR_RW_FUNCS(hcptr, HCPTR)
233DEFINE_COPROCR_RW_FUNCS(cntfrq, CNTFRQ)
234DEFINE_COPROCR_RW_FUNCS(cnthctl, CNTHCTL)
235DEFINE_COPROCR_RW_FUNCS(mair0, MAIR0)
236DEFINE_COPROCR_RW_FUNCS(mair1, MAIR1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000237DEFINE_COPROCR_RW_FUNCS(hmair0, HMAIR0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100238DEFINE_COPROCR_RW_FUNCS(ttbcr, TTBCR)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000239DEFINE_COPROCR_RW_FUNCS(htcr, HTCR)
Soby Mathewc6820d12016-05-09 17:49:55 +0100240DEFINE_COPROCR_RW_FUNCS(ttbr0, TTBR0)
241DEFINE_COPROCR_RW_FUNCS_64(ttbr0, TTBR0_64)
242DEFINE_COPROCR_RW_FUNCS(ttbr1, TTBR1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000243DEFINE_COPROCR_RW_FUNCS_64(httbr, HTTBR_64)
Soby Mathewc6820d12016-05-09 17:49:55 +0100244DEFINE_COPROCR_RW_FUNCS(vpidr, VPIDR)
245DEFINE_COPROCR_RW_FUNCS(vmpidr, VMPIDR)
246DEFINE_COPROCR_RW_FUNCS_64(vttbr, VTTBR_64)
247DEFINE_COPROCR_RW_FUNCS_64(ttbr1, TTBR1_64)
248DEFINE_COPROCR_RW_FUNCS_64(cntvoff, CNTVOFF_64)
249DEFINE_COPROCR_RW_FUNCS(csselr, CSSELR)
David Cunadofee86532017-04-13 22:38:29 +0100250DEFINE_COPROCR_RW_FUNCS(hstr, HSTR)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000251DEFINE_COPROCR_RW_FUNCS(cnthp_ctl_el2, CNTHP_CTL)
252DEFINE_COPROCR_RW_FUNCS(cnthp_tval_el2, CNTHP_TVAL)
253DEFINE_COPROCR_RW_FUNCS_64(cnthp_cval_el2, CNTHP_CVAL_64)
Soby Mathewc6820d12016-05-09 17:49:55 +0100254
Antonio Nino Diazdc4ed3d2018-11-23 13:54:00 +0000255#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
256 CNTP_CTL_ENABLE_MASK)
257#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
258 CNTP_CTL_IMASK_MASK)
259#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
260 CNTP_CTL_ISTATUS_MASK)
261
262#define set_cntp_ctl_enable(x) ((x) |= U(1) << CNTP_CTL_ENABLE_SHIFT)
263#define set_cntp_ctl_imask(x) ((x) |= U(1) << CNTP_CTL_IMASK_SHIFT)
264
265#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
266#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
267
Soby Mathewc6820d12016-05-09 17:49:55 +0100268DEFINE_COPROCR_RW_FUNCS(icc_sre_el1, ICC_SRE)
269DEFINE_COPROCR_RW_FUNCS(icc_sre_el2, ICC_HSRE)
270DEFINE_COPROCR_RW_FUNCS(icc_sre_el3, ICC_MSRE)
271DEFINE_COPROCR_RW_FUNCS(icc_pmr_el1, ICC_PMR)
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100272DEFINE_COPROCR_RW_FUNCS(icc_rpr_el1, ICC_RPR)
Soby Mathewc6820d12016-05-09 17:49:55 +0100273DEFINE_COPROCR_RW_FUNCS(icc_igrpen1_el3, ICC_MGRPEN1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000274DEFINE_COPROCR_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100275DEFINE_COPROCR_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0)
276DEFINE_COPROCR_RW_FUNCS(icc_hppir0_el1, ICC_HPPIR0)
277DEFINE_COPROCR_RW_FUNCS(icc_hppir1_el1, ICC_HPPIR1)
278DEFINE_COPROCR_RW_FUNCS(icc_iar0_el1, ICC_IAR0)
279DEFINE_COPROCR_RW_FUNCS(icc_iar1_el1, ICC_IAR1)
280DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0)
281DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100282DEFINE_COPROCR_RW_FUNCS_64(icc_sgi0r_el1, ICC_SGI0R_EL1_64)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000283DEFINE_COPROCR_WRITE_FUNC_64(icc_sgi1r, ICC_SGI1R_EL1_64)
Soby Mathewc6820d12016-05-09 17:49:55 +0100284
David Cunado5f55e282016-10-31 17:37:34 +0000285DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR)
David Cunadoc14b08e2016-11-25 00:21:59 +0000286DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL)
David Cunado5f55e282016-10-31 17:37:34 +0000287DEFINE_COPROCR_READ_FUNC(pmcr, PMCR)
288
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000289/*
290 * Address translation
291 */
292DEFINE_COPROCR_WRITE_FUNC(ats1cpr, ATS1CPR)
293DEFINE_COPROCR_WRITE_FUNC(ats1hr, ATS1HR)
Douglas Raillard77414632018-08-21 12:54:45 +0100294DEFINE_COPROCR_RW_FUNCS_64(par, PAR_64)
295
Etienne Carriere70a004b2017-11-05 22:56:03 +0100296DEFINE_COPROCR_RW_FUNCS(nsacr, NSACR)
297
298/* AArch32 coproc registers for 32bit MMU descriptor support */
299DEFINE_COPROCR_RW_FUNCS(prrr, PRRR)
300DEFINE_COPROCR_RW_FUNCS(nmrr, NMRR)
301DEFINE_COPROCR_RW_FUNCS(dacr, DACR)
302
Alexei Fedorov7e6306b2020-07-14 08:17:56 +0100303/* Coproc registers for 32bit AMU support */
304DEFINE_COPROCR_READ_FUNC(amcfgr, AMCFGR)
305DEFINE_COPROCR_READ_FUNC(amcgcr, AMCGCR)
306
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100307DEFINE_COPROCR_RW_FUNCS(amcntenset0, AMCNTENSET0)
308DEFINE_COPROCR_RW_FUNCS(amcntenset1, AMCNTENSET1)
309DEFINE_COPROCR_RW_FUNCS(amcntenclr0, AMCNTENCLR0)
310DEFINE_COPROCR_RW_FUNCS(amcntenclr1, AMCNTENCLR1)
311
Alexei Fedorov7e6306b2020-07-14 08:17:56 +0100312/* Coproc registers for 64bit AMU support */
Dimitris Papastamoseaf3e6d2017-11-28 13:47:06 +0000313DEFINE_COPROCR_RW_FUNCS_64(amevcntr00, AMEVCNTR00)
314DEFINE_COPROCR_RW_FUNCS_64(amevcntr01, AMEVCNTR01)
315DEFINE_COPROCR_RW_FUNCS_64(amevcntr02, AMEVCNTR02)
316DEFINE_COPROCR_RW_FUNCS_64(amevcntr03, AMEVCNTR03)
317
Soby Mathewc6820d12016-05-09 17:49:55 +0100318/*
319 * TLBI operation prototypes
320 */
321DEFINE_TLBIOP_FUNC(all, TLBIALL)
322DEFINE_TLBIOP_FUNC(allis, TLBIALLIS)
323DEFINE_TLBIOP_PARAM_FUNC(mva, TLBIMVA)
324DEFINE_TLBIOP_PARAM_FUNC(mvaa, TLBIMVAA)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000325DEFINE_TLBIOP_PARAM_FUNC(mvaais, TLBIMVAAIS)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100326DEFINE_TLBIOP_PARAM_FUNC(mvahis, TLBIMVAHIS)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000327
328/*
329 * BPI operation prototypes.
330 */
331DEFINE_BPIOP_FUNC(allis, BPIALLIS)
Soby Mathewc6820d12016-05-09 17:49:55 +0100332
333/*
334 * DC operation prototypes
335 */
336DEFINE_DCOP_PARAM_FUNC(civac, DCCIMVAC)
337DEFINE_DCOP_PARAM_FUNC(ivac, DCIMVAC)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000338#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
339DEFINE_DCOP_PARAM_FUNC(cvac, DCCIMVAC)
340#else
Soby Mathewc6820d12016-05-09 17:49:55 +0100341DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000342#endif
Soby Mathewc6820d12016-05-09 17:49:55 +0100343
Madhukar Pappireddy90d65322019-10-30 14:24:39 -0500344/*
345 * DynamIQ Shared Unit power management
346 */
347DEFINE_COPROCR_RW_FUNCS(clusterpwrdn, CLUSTERPWRDN)
348
Soby Mathewc6820d12016-05-09 17:49:55 +0100349/* Previously defined accessor functions with incomplete register names */
350#define dsb() dsbsy()
Etienne Carrierea2579862017-11-05 22:57:29 +0100351#define dmb() dmbsy()
Soby Mathewc6820d12016-05-09 17:49:55 +0100352
Jeenu Viswambharan1aa2db32018-09-05 14:23:27 +0100353/* dmb ld is not valid for armv7/thumb machines, so alias it to dmb */
354#if ARM_ARCH_MAJOR == 7
355#define dmbld() dmb()
356#endif
357
Soby Mathewc6820d12016-05-09 17:49:55 +0100358#define IS_IN_SECURE() \
359 (GET_NS_BIT(read_scr()) == 0)
360
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100361#define IS_IN_HYP() (GET_M32(read_cpsr()) == MODE32_hyp)
362#define IS_IN_SVC() (GET_M32(read_cpsr()) == MODE32_svc)
363#define IS_IN_MON() (GET_M32(read_cpsr()) == MODE32_mon)
364#define IS_IN_EL2() IS_IN_HYP()
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000365/* If EL3 is AArch32, then secure PL1 and monitor mode correspond to EL3 */
Soby Mathewc6820d12016-05-09 17:49:55 +0100366#define IS_IN_EL3() \
367 ((GET_M32(read_cpsr()) == MODE32_mon) || \
368 (IS_IN_SECURE() && (GET_M32(read_cpsr()) != MODE32_usr)))
369
Douglas Raillard77414632018-08-21 12:54:45 +0100370static inline unsigned int get_current_el(void)
371{
372 if (IS_IN_EL3()) {
373 return 3U;
374 } else if (IS_IN_EL2()) {
375 return 2U;
376 } else {
377 return 1U;
378 }
379}
380
Soby Mathewc6820d12016-05-09 17:49:55 +0100381/* Macros for compatibility with AArch64 system registers */
382#define read_mpidr_el1() read_mpidr()
383
384#define read_scr_el3() read_scr()
385#define write_scr_el3(_v) write_scr(_v)
386
387#define read_hcr_el2() read_hcr()
388#define write_hcr_el2(_v) write_hcr(_v)
389
390#define read_cpacr_el1() read_cpacr()
391#define write_cpacr_el1(_v) write_cpacr(_v)
392
393#define read_cntfrq_el0() read_cntfrq()
394#define write_cntfrq_el0(_v) write_cntfrq(_v)
395#define read_isr_el1() read_isr()
396
397#define read_cntpct_el0() read64_cntpct()
398
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100399#define read_ctr_el0() read_ctr()
400
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000401#define write_icc_sgi0r_el1(_v) write64_icc_sgi0r_el1(_v)
402
403#define read_daif() read_cpsr()
404#define write_daif(flags) write_cpsr(flags)
405
406#define read_cnthp_cval_el2() read64_cnthp_cval_el2()
407#define write_cnthp_cval_el2(v) write64_cnthp_cval_el2(v)
408
409#define read_amcntenset0_el0() read_amcntenset0()
410#define read_amcntenset1_el0() read_amcntenset1()
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100411
Antonio Nino Diazb4e3e4b2018-11-23 15:04:01 +0000412/* Helper functions to manipulate CPSR */
413static inline void enable_irq(void)
414{
415 /*
416 * The compiler memory barrier will prevent the compiler from
417 * scheduling non-volatile memory access after the write to the
418 * register.
419 *
420 * This could happen if some initialization code issues non-volatile
421 * accesses to an area used by an interrupt handler, in the assumption
422 * that it is safe as the interrupts are disabled at the time it does
423 * that (according to program order). However, non-volatile accesses
424 * are not necessarily in program order relatively with volatile inline
425 * assembly statements (and volatile accesses).
426 */
427 COMPILER_BARRIER();
428 __asm__ volatile ("cpsie i");
429 isb();
430}
431
432static inline void enable_serror(void)
433{
434 COMPILER_BARRIER();
435 __asm__ volatile ("cpsie a");
436 isb();
437}
438
439static inline void enable_fiq(void)
440{
441 COMPILER_BARRIER();
442 __asm__ volatile ("cpsie f");
443 isb();
444}
445
446static inline void disable_irq(void)
447{
448 COMPILER_BARRIER();
449 __asm__ volatile ("cpsid i");
450 isb();
451}
452
453static inline void disable_serror(void)
454{
455 COMPILER_BARRIER();
456 __asm__ volatile ("cpsid a");
457 isb();
458}
459
460static inline void disable_fiq(void)
461{
462 COMPILER_BARRIER();
463 __asm__ volatile ("cpsid f");
464 isb();
465}
466
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000467#endif /* ARCH_HELPERS_H */