blob: 47a245a6c43c75646678d5819b6feb27cd7c39ef [file] [log] [blame]
Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arm_gic.h>
32#include <assert.h>
33#include <bl_common.h>
34#include <console.h>
35#include <debug.h>
Antonio Nino Diaz2361fcc2016-05-05 15:25:02 +010036#include <generic_delay_timer.h>
Tony Xief6118cc2016-01-15 17:17:32 +080037#include <mmio.h>
38#include <platform.h>
39#include <plat_private.h>
40#include <platform_def.h>
41
42/*******************************************************************************
43 * Declarations of linker defined symbols which will help us find the layout
44 * of trusted SRAM
45 ******************************************************************************/
46unsigned long __RO_START__;
47unsigned long __RO_END__;
48
49unsigned long __COHERENT_RAM_START__;
50unsigned long __COHERENT_RAM_END__;
51
52/*
53 * The next 2 constants identify the extents of the code & RO data region.
54 * These addresses are used by the MMU setup code and therefore they must be
55 * page-aligned. It is the responsibility of the linker script to ensure that
56 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
57 */
58#define BL31_RO_BASE (unsigned long)(&__RO_START__)
59#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
60
61/*
62 * The next 2 constants identify the extents of the coherent memory region.
63 * These addresses are used by the MMU setup code and therefore they must be
64 * page-aligned. It is the responsibility of the linker script to ensure that
65 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
66 * refer to page-aligned addresses.
67 */
68#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
69#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
70
71static entry_point_info_t bl32_ep_info;
72static entry_point_info_t bl33_ep_info;
73
74/*******************************************************************************
75 * Return a pointer to the 'entry_point_info' structure of the next image for
76 * the security state specified. BL33 corresponds to the non-secure image type
77 * while BL32 corresponds to the secure image type. A NULL pointer is returned
78 * if the image does not exist.
79 ******************************************************************************/
80entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
81{
82 entry_point_info_t *next_image_info;
83
84 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
85
86 /* None of the images on this platform can have 0x0 as the entrypoint */
87 if (next_image_info->pc)
88 return next_image_info;
89 else
90 return NULL;
91}
92
93/*******************************************************************************
94 * Perform any BL3-1 early platform setup. Here is an opportunity to copy
95 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
96 * are lost (potentially). This needs to be done before the MMU is initialized
97 * so that the memory layout can be used while creating page tables.
98 * BL2 has flushed this information to memory, so we are guaranteed to pick up
99 * good data.
100 ******************************************************************************/
101void bl31_early_platform_setup(bl31_params_t *from_bl2,
102 void *plat_params_from_bl2)
103{
104 console_init(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK,
105 PLAT_RK_UART_BAUDRATE);
106
107 VERBOSE("bl31_setup\n");
108
109 /* Passing a NULL context is a critical programming error */
110 assert(from_bl2);
111
112 assert(from_bl2->h.type == PARAM_BL31);
113 assert(from_bl2->h.version >= VERSION_1);
114
115 bl32_ep_info = *from_bl2->bl32_ep_info;
116 bl33_ep_info = *from_bl2->bl33_ep_info;
117
118 /*
119 * The code for resuming cpu from suspend must be excuted in pmusram.
120 * Copy the code into pmusram.
121 */
122 plat_rockchip_pmusram_prepare();
Caesar Wang3e3c5b02016-05-25 19:03:04 +0800123
124 /* there may have some board sepcific message need to initialize */
125 params_early_setup(plat_params_from_bl2);
Tony Xief6118cc2016-01-15 17:17:32 +0800126}
127
128/*******************************************************************************
129 * Perform any BL3-1 platform setup code
130 ******************************************************************************/
131void bl31_platform_setup(void)
132{
Antonio Nino Diaz2361fcc2016-05-05 15:25:02 +0100133 generic_delay_timer_init();
Tony Xief6118cc2016-01-15 17:17:32 +0800134 plat_rockchip_soc_init();
135
136 /* Initialize the gic cpu and distributor interfaces */
137 plat_rockchip_gic_driver_init();
138 plat_rockchip_gic_init();
139 plat_rockchip_pmu_init();
140}
141
142/*******************************************************************************
143 * Perform the very early platform specific architectural setup here. At the
144 * moment this is only intializes the mmu in a quick and dirty way.
145 ******************************************************************************/
146void bl31_plat_arch_setup(void)
147{
148 plat_cci_init();
149 plat_cci_enable();
150 plat_configure_mmu_el3(BL31_RO_BASE,
151 (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
152 BL31_RO_BASE,
153 BL31_RO_LIMIT,
154 BL31_COHERENT_RAM_BASE,
155 BL31_COHERENT_RAM_LIMIT);
156}