blob: 43e0eb893ca3d11c9a45fe75d89871319548b042 [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +00001/*
David Cunado2e36de82017-01-19 10:26:16 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#ifndef __ARM_DEF_H__
31#define __ARM_DEF_H__
32
Soby Mathewfec4eb72015-07-01 16:16:20 +010033#include <arch.h>
Dan Handley9df48042015-03-19 18:58:55 +000034#include <common_def.h>
35#include <platform_def.h>
Juan Castillo9b265a82015-05-07 14:52:44 +010036#include <tbbr_img_def.h>
Douglas Raillard30a26942017-03-08 16:49:31 +000037#include <utils.h>
Antonio Nino Diaz719bf852017-02-23 17:22:58 +000038#include <xlat_tables_defs.h>
Dan Handley9df48042015-03-19 18:58:55 +000039
40
41/******************************************************************************
42 * Definitions common to all ARM standard platforms
43 *****************************************************************************/
44
Juan Castillo7d199412015-12-14 09:35:25 +000045/* Special value used to verify platform parameters from BL2 to BL31 */
Dan Handley9df48042015-03-19 18:58:55 +000046#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
47
Soby Mathewa869de12015-05-08 10:18:59 +010048#define ARM_SYSTEM_COUNT 1
Dan Handley9df48042015-03-19 18:58:55 +000049
50#define ARM_CACHE_WRITEBACK_SHIFT 6
51
Soby Mathewfec4eb72015-07-01 16:16:20 +010052/*
53 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
54 * power levels have a 1:1 mapping with the MPIDR affinity levels.
55 */
56#define ARM_PWR_LVL0 MPIDR_AFFLVL0
57#define ARM_PWR_LVL1 MPIDR_AFFLVL1
Soby Mathewa869de12015-05-08 10:18:59 +010058#define ARM_PWR_LVL2 MPIDR_AFFLVL2
Soby Mathewfec4eb72015-07-01 16:16:20 +010059
60/*
61 * Macros for local power states in ARM platforms encoded by State-ID field
62 * within the power-state parameter.
63 */
64/* Local power state for power domains in Run state. */
65#define ARM_LOCAL_STATE_RUN 0
66/* Local power state for retention. Valid only for CPU power domains */
67#define ARM_LOCAL_STATE_RET 1
68/* Local power state for OFF/power-down. Valid for CPU and cluster power
69 domains */
70#define ARM_LOCAL_STATE_OFF 2
71
Dan Handley9df48042015-03-19 18:58:55 +000072/* Memory location options for TSP */
73#define ARM_TRUSTED_SRAM_ID 0
74#define ARM_TRUSTED_DRAM_ID 1
75#define ARM_DRAM_ID 2
76
77/* The first 4KB of Trusted SRAM are used as shared memory */
78#define ARM_TRUSTED_SRAM_BASE 0x04000000
79#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
80#define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
81
82/* The remaining Trusted SRAM is used to load the BL images */
83#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
84 ARM_SHARED_RAM_SIZE)
85#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
86 ARM_SHARED_RAM_SIZE)
87
88/*
89 * The top 16MB of DRAM1 is configured as secure access only using the TZC
90 * - SCP TZC DRAM: If present, DRAM reserved for SCP use
91 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
92 */
David Cunado2e36de82017-01-19 10:26:16 +000093#define ARM_TZC_DRAM1_SIZE ULL(0x01000000)
Dan Handley9df48042015-03-19 18:58:55 +000094
95#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
96 ARM_DRAM1_SIZE - \
97 ARM_SCP_TZC_DRAM1_SIZE)
98#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
99#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
100 ARM_SCP_TZC_DRAM1_SIZE - 1)
101
102#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
103 ARM_DRAM1_SIZE - \
104 ARM_TZC_DRAM1_SIZE)
105#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
106 ARM_SCP_TZC_DRAM1_SIZE)
107#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
108 ARM_AP_TZC_DRAM1_SIZE - 1)
109
110
111#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
112#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
113 ARM_TZC_DRAM1_SIZE)
114#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
115 ARM_NS_DRAM1_SIZE - 1)
116
David Cunado2e36de82017-01-19 10:26:16 +0000117#define ARM_DRAM1_BASE ULL(0x80000000)
118#define ARM_DRAM1_SIZE ULL(0x80000000)
Dan Handley9df48042015-03-19 18:58:55 +0000119#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
120 ARM_DRAM1_SIZE - 1)
121
David Cunado2e36de82017-01-19 10:26:16 +0000122#define ARM_DRAM2_BASE ULL(0x880000000)
Dan Handley9df48042015-03-19 18:58:55 +0000123#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
124#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
125 ARM_DRAM2_SIZE - 1)
126
127#define ARM_IRQ_SEC_PHY_TIMER 29
128
129#define ARM_IRQ_SEC_SGI_0 8
130#define ARM_IRQ_SEC_SGI_1 9
131#define ARM_IRQ_SEC_SGI_2 10
132#define ARM_IRQ_SEC_SGI_3 11
133#define ARM_IRQ_SEC_SGI_4 12
134#define ARM_IRQ_SEC_SGI_5 13
135#define ARM_IRQ_SEC_SGI_6 14
136#define ARM_IRQ_SEC_SGI_7 15
137
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000138/*
139 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
140 * terminology. On a GICv2 system or mode, the lists will be merged and treated
141 * as Group 0 interrupts.
142 */
143#define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \
144 ARM_IRQ_SEC_SGI_1, \
145 ARM_IRQ_SEC_SGI_2, \
146 ARM_IRQ_SEC_SGI_3, \
147 ARM_IRQ_SEC_SGI_4, \
148 ARM_IRQ_SEC_SGI_5, \
149 ARM_IRQ_SEC_SGI_7
150
151#define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \
152 ARM_IRQ_SEC_SGI_6
153
Dan Handley9df48042015-03-19 18:58:55 +0000154#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
155 ARM_SHARED_RAM_BASE, \
156 ARM_SHARED_RAM_SIZE, \
Juan Castillo2e86cb12016-01-13 15:01:09 +0000157 MT_DEVICE | MT_RW | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +0000158
159#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
160 ARM_NS_DRAM1_BASE, \
161 ARM_NS_DRAM1_SIZE, \
162 MT_MEMORY | MT_RW | MT_NS)
163
164#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
165 TSP_SEC_MEM_BASE, \
166 TSP_SEC_MEM_SIZE, \
167 MT_MEMORY | MT_RW | MT_SECURE)
168
David Wang0ba499f2016-03-07 11:02:57 +0800169#if ARM_BL31_IN_DRAM
170#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
171 BL31_BASE, \
172 PLAT_ARM_MAX_BL31_SIZE, \
173 MT_MEMORY | MT_RW | MT_SECURE)
174#endif
Dan Handley9df48042015-03-19 18:58:55 +0000175
176/*
177 * The number of regions like RO(code), coherent and data required by
178 * different BL stages which need to be mapped in the MMU.
179 */
180#if USE_COHERENT_MEM
181#define ARM_BL_REGIONS 3
182#else
183#define ARM_BL_REGIONS 2
184#endif
185
186#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
187 ARM_BL_REGIONS)
188
189/* Memory mapped Generic timer interfaces */
190#define ARM_SYS_CNTCTL_BASE 0x2a430000
191#define ARM_SYS_CNTREAD_BASE 0x2a800000
192#define ARM_SYS_TIMCTL_BASE 0x2a810000
193
194#define ARM_CONSOLE_BAUDRATE 115200
195
Juan Castillob6132f12015-10-06 14:01:35 +0100196/* Trusted Watchdog constants */
197#define ARM_SP805_TWDG_BASE 0x2a490000
198#define ARM_SP805_TWDG_CLK_HZ 32768
199/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
200 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
201#define ARM_TWDG_TIMEOUT_SEC 128
202#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
203 ARM_TWDG_TIMEOUT_SEC)
204
Dan Handley9df48042015-03-19 18:58:55 +0000205/******************************************************************************
206 * Required platform porting definitions common to all ARM standard platforms
207 *****************************************************************************/
208
Antonio Nino Diazf6601042016-12-13 13:48:31 +0000209#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
210#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
Dan Handley9df48042015-03-19 18:58:55 +0000211
Soby Mathewfec4eb72015-07-01 16:16:20 +0100212/*
213 * This macro defines the deepest retention state possible. A higher state
214 * id will represent an invalid or a power down state.
215 */
216#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
217
218/*
219 * This macro defines the deepest power down states possible. Any state ID
220 * higher than this is invalid.
221 */
222#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
223
Dan Handley9df48042015-03-19 18:58:55 +0000224/*
225 * Some data must be aligned on the biggest cache line size in the platform.
226 * This is known only to the platform as it might have a combination of
227 * integrated and external caches.
228 */
229#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT)
230
Dan Handley9df48042015-03-19 18:58:55 +0000231
232/*******************************************************************************
233 * BL1 specific defines.
234 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
235 * addresses.
236 ******************************************************************************/
237#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
238#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
239 + PLAT_ARM_TRUSTED_ROM_SIZE)
240/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000241 * Put BL1 RW at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000242 */
Dan Handley9df48042015-03-19 18:58:55 +0000243#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
244 ARM_BL_RAM_SIZE - \
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000245 PLAT_ARM_MAX_BL1_RW_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000246#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
247
248/*******************************************************************************
249 * BL2 specific defines.
250 ******************************************************************************/
David Wang0ba499f2016-03-07 11:02:57 +0800251#if ARM_BL31_IN_DRAM
252/*
253 * BL31 is loaded in the DRAM.
254 * Put BL2 just below BL1.
255 */
256#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
257#define BL2_LIMIT BL1_RW_BASE
258#else
Dan Handley9df48042015-03-19 18:58:55 +0000259/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000260 * Put BL2 just below BL31.
Dan Handley9df48042015-03-19 18:58:55 +0000261 */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000262#define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000263#define BL2_LIMIT BL31_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800264#endif
Dan Handley9df48042015-03-19 18:58:55 +0000265
266/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000267 * BL31 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000268 ******************************************************************************/
David Wang0ba499f2016-03-07 11:02:57 +0800269#if ARM_BL31_IN_DRAM
270/*
271 * Put BL31 at the bottom of TZC secured DRAM
272 */
273#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
274#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
275 PLAT_ARM_MAX_BL31_SIZE)
276#else
Dan Handley9df48042015-03-19 18:58:55 +0000277/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000278 * Put BL31 at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000279 */
280#define BL31_BASE (ARM_BL_RAM_BASE + \
281 ARM_BL_RAM_SIZE - \
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000282 PLAT_ARM_MAX_BL31_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000283#define BL31_PROGBITS_LIMIT BL1_RW_BASE
284#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
David Wang0ba499f2016-03-07 11:02:57 +0800285#endif
Dan Handley9df48042015-03-19 18:58:55 +0000286
287/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000288 * BL32 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000289 ******************************************************************************/
290/*
291 * On ARM standard platforms, the TSP can execute from Trusted SRAM,
292 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
293 * controller.
294 */
David Wang0ba499f2016-03-07 11:02:57 +0800295#if ARM_BL31_IN_DRAM
296# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
297 PLAT_ARM_MAX_BL31_SIZE)
298# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \
299 PLAT_ARM_MAX_BL31_SIZE)
300# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \
301 PLAT_ARM_MAX_BL31_SIZE)
302# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
303 ARM_AP_TZC_DRAM1_SIZE)
304#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
Dan Handley9df48042015-03-19 18:58:55 +0000305# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
306# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
307# define TSP_PROGBITS_LIMIT BL2_BASE
308# define BL32_BASE ARM_BL_RAM_BASE
309# define BL32_LIMIT BL31_BASE
310#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
311# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
312# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
313# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
314# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
315 + (1 << 21))
316#elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
317# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
318# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
319# define BL32_BASE ARM_AP_TZC_DRAM1_BASE
320# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
321 ARM_AP_TZC_DRAM1_SIZE)
322#else
323# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
324#endif
325
Soby Mathew0d268dc2016-07-11 14:13:56 +0100326/* BL32 is mandatory in AArch32 */
327#ifndef AARCH32
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100328#ifdef SPD_none
329#undef BL32_BASE
330#endif /* SPD_none */
Soby Mathew0d268dc2016-07-11 14:13:56 +0100331#endif
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100332
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100333/*******************************************************************************
334 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
335 ******************************************************************************/
336#define BL2U_BASE BL2_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800337#if ARM_BL31_IN_DRAM
338#define BL2U_LIMIT BL1_RW_BASE
339#else
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100340#define BL2U_LIMIT BL31_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800341#endif
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100342#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
Yatharth Kocharf11b29a2016-02-01 11:04:46 +0000343#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000)
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100344
Dan Handley9df48042015-03-19 18:58:55 +0000345/*
346 * ID of the secure physical generic timer interrupt used by the TSP.
347 */
348#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
349
350
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100351/*
352 * One cache line needed for bakery locks on ARM platforms
353 */
354#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
355
356
Dan Handley9df48042015-03-19 18:58:55 +0000357#endif /* __ARM_DEF_H__ */