| Jit Loon Lim | 65b49f4 | 2025-02-10 15:15:31 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2024, Intel Corporation. All rights reserved. |
| 3 | * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | /dts-v1/; |
| 9 | |
| 10 | / { |
| 11 | model = "ALTERA SOCFPGA AGILEX5"; |
| 12 | compatible = "arm,altera socfpga-agilex5"; |
| 13 | owner = "jit.loon.lim@intel.com"; |
| 14 | interrupt-parent = <&gic>; |
| 15 | #address-cells = <1>; |
| 16 | #size-cells = <1>; |
| 17 | |
| 18 | psci { |
| 19 | compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; |
| 20 | method = "smc"; |
| 21 | |
| 22 | cpu_on = <0xdeadc0de>; |
| 23 | }; |
| 24 | |
| 25 | cpus { |
| 26 | #address-cells = <1>; |
| 27 | #size-cells = <0>; |
| 28 | enable-method = "psci"; |
| 29 | cpu@0 { |
| 30 | device_type = "cpu"; |
| 31 | compatible = "arm,cortex-a5"; |
| 32 | reg = <0>; |
| 33 | }; |
| 34 | cpu@1 { |
| 35 | device_type = "cpu"; |
| 36 | compatible = "arm,cortex-a5"; |
| 37 | reg = <1>; |
| 38 | }; |
| 39 | cpu@2 { |
| 40 | device_type = "cpu"; |
| 41 | compatible = "arm,cortex-a5"; |
| 42 | reg = <2>; |
| 43 | }; |
| 44 | cpu@3 { |
| 45 | device_type = "cpu"; |
| 46 | compatible = "arm,cortex-a5"; |
| 47 | reg = <3>; |
| 48 | }; |
| 49 | }; |
| 50 | |
| 51 | memory@80000000 { |
| 52 | device_type = "memory"; |
| 53 | reg = <0x80000000 0x90000000>; |
| 54 | }; |
| 55 | |
| 56 | gic: interrupt-controller@2c010000 { |
| 57 | compatible = "arm,gic-600", "arm,gic-v3"; |
| 58 | #address-cells = <2>; |
| 59 | #interrupt-cells = <3>; |
| 60 | #size-cells = <1>; |
| 61 | #ranges; |
| 62 | interrupt-controller; |
| 63 | reg = <0x1D000000 0>, /* GICD */ |
| 64 | <0x1D060000 0>; /* GICR */ |
| 65 | interrupts = <0x1 0x9 0x4>; |
| 66 | }; |
| 67 | |
| 68 | serial0: uart@1a200000 { |
| 69 | compatible = "arm,console-16550"; |
| 70 | reg = <0x10C02000 0x1000>; |
| 71 | interrupt-parent = <&gic>; |
| 72 | interrupts = <0 8 0xf04>; |
| 73 | clock-frequency = <100000000>; |
| 74 | uart-baudrate = <115200>; |
| 75 | }; |
| 76 | |
| 77 | timer0: timer@1a040000 { |
| 78 | compatible = "arm,armv7-timer-mem"; |
| 79 | #address-cells = <1>; |
| 80 | #size-cells = <1>; |
| 81 | ranges; |
| 82 | reg = <0x1a040000 0x1000>; |
| 83 | clock-frequency = <7500000>; |
| 84 | |
| 85 | frame@1a050000 { |
| 86 | frame-number = <0>; |
| 87 | interrupts = <0 2 0xf04>; |
| 88 | reg = <0x1a050000 0x1000>; |
| 89 | }; |
| 90 | }; |
| 91 | |
| 92 | }; |