blob: 44284f6fe02cb4f0fca1ec770b1af2946aae3700 [file] [log] [blame]
Bryan O'Donoghue1c7bbca2018-06-20 16:56:31 +01001/*
2 * Copyright 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __IMX_IO_MUX_H__
8#define __IMX_IO_MUX_H__
9
10#include <stdint.h>
11
12/*
13 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
14 * Section 8.2.7 IOMUXC Memory Map/Register Definition
15 */
16
17#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_OFFSET 0x0014
18#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_OFFSET 0x0018
19#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_OFFSET 0x001C
20#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_OFFSET 0x0020
21#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_OFFSET 0x0024
22#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_OFFSET 0x0028
23#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET 0x002C
24#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_OFFSET 0x0030
25
26#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_OFFSET 0x0034
27#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_OFFSET 0x0038
28#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_OFFSET 0x003C
29#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_OFFSET 0x0040
30#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_OFFSET 0x0044
31#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_OFFSET 0x0048
32#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_OFFSET 0x004C
33#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_OFFSET 0x0050
34#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_OFFSET 0x0054
35#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_OFFSET 0x0058
36#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_OFFSET 0x005C
37#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_OFFSET 0x0060
38#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_OFFSET 0x0064
39#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_OFFSET 0x0068
40#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_OFFSET 0x006C
41#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_OFFSET 0x0070
42
43#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_OFFSET 0x0074
44#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_OFFSET 0x0078
45#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_OFFSET 0x007C
46#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_OFFSET 0x0080
47#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_OFFSET 0x0084
48#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_OFFSET 0x0088
49#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_OFFSET 0x008C
50#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_OFFSET 0x0090
51
52#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_OFFSET 0x0094
53#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_OFFSET 0x0098
54#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_OFFSET 0x009C
55#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_OFFSET 0x00A0
56#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_OFFSET 0x00A4
57#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_OFFSET 0x00A8
58#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_OFFSET 0x00AC
59#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_OFFSET 0x00B0
60
61#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_OFFSET 0x00B4
62#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_OFFSET 0x00B8
63#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_OFFSET 0x00BC
64#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_OFFSET 0x00C0
65#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_OFFSET 0x00C4
66#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_OFFSET 0x00C8
67#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_OFFSET 0x00CC
68#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_OFFSET 0x00D0
69#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_OFFSET 0x00D4
70#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_OFFSET 0x00D8
71#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_OFFSET 0x00DC
72#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_OFFSET 0x00E0
73#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_OFFSET 0x00E4
74#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_OFFSET 0x00E8
75#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_OFFSET 0x00EC
76#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_OFFSET 0x00F0
77#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_OFFSET 0x00F4
78#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_OFFSET 0x00F8
79#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_OFFSET 0x00FC
80#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_OFFSET 0x0100
81#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_OFFSET 0x0104
82#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_OFFSET 0x0108
83#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_OFFSET 0x010C
84#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_OFFSET 0x0110
85#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_OFFSET 0x0114
86#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_OFFSET 0x0118
87#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_OFFSET 0x011C
88#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_OFFSET 0x0120
89#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_OFFSET 0x0124
90
91#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET 0x0128
92#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA 0x00
93#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT1_I2C1_SCL BIT(0)
94#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT2_PMIC_READY BIT(1)
95#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT3_ECSPI1_SS1 (BIT(1) | BIT(0))
96#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT4_ENET2_1588_EVENT0_IN BIT(3)
97#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT5_GPIO4_IO0 (BIT(2) | BIT(0))
98#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT6_ENET1_MDIO (BIT(2) | BIT(1))
99#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_SION BIT(3)
100
101#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET 0x012C
102#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA 0x00
103#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT1_I2C1_SDA BIT(0)
104#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT2_SAI3_MCLK BIT(1)
105#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT3_ECSPI1_SS2 (BIT(1) | BIT(0))
106#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT4_ENET2_1588_EVENT0_OUT BIT(3)
107#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT5_GPIO4_IO1 (BIT(2) | BIT(0))
108#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT6_ENET1_MDC (BIT(2) | BIT(1))
109#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_SION BIT(3)
110
111#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_OFFSET 0x0130
112#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_OFFSET 0x0134
113#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_OFFSET 0x0138
114#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_OFFSET 0x013C
115#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_OFFSET 0x0140
116#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_OFFSET 0x0144
117
118#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_OFFSET 0x0148
119#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_OFFSET 0x014C
120#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_OFFSET 0x0150
121#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_OFFSET 0x0154
122#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_OFFSET 0x0158
123#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_OFFSET 0x015C
124#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET 0x0160
125#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET 0x0164
126
127#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET 0x0168
128#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT0_ECSPI1_SCLK 0x00
129#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA BIT(0)
130#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT2_SD2_DATA4 BIT(1)
131#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT3_CSI_DATA2 (BIT(1) | BIT(0))
132#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT5_GPIO4_IO16 (BIT(2) | BIT(0))
133#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT6_EPDC_PWR_COM (BIT(2) | (BIT(1))
134
135#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET 0x016C
136#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT0_ECSPI1_MOSI 0x00
137#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA BIT(0)
138#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT2_SD2_DATA5 BIT(1)
139#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT3_CSI_DATA3 (BIT(1) | BIT(0))
140#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT5_GPIO4_IO17 (BIT(2) | BIT(0))
141#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT6_EPDC_PWR_STAT (BIT(2) | (BIT(1))
142
143#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_OFFSET 0x0170
144#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_OFFSET 0x0174
145#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_OFFSET 0x0178
146#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_OFFSET 0x017C
147#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_OFFSET 0x0180
148#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_OFFSET 0x0184
149
150#define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_OFFSET 0x0188
151#define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_OFFSET 0x018C
152#define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_OFFSET 0x0190
153#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_OFFSET 0x0194
154#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_OFFSET 0x0198
155#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_OFFSET 0x019C
156#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_OFFSET 0x01A0
157#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_OFFSET 0x01A4
158#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_OFFSET 0x01A8
159#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_OFFSET 0x01AC
160#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_OFFSET 0x01B0
161#define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_OFFSET 0x01B4
162#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_OFFSET 0x01B8
163#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_OFFSET 0x01BC
164#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_OFFSET 0x01C0
165#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_OFFSET 0x01C4
166#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_OFFSET 0x01C8
167#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_OFFSET 0x01CC
168#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET 0x01D0
169#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET 0x01D4
170#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET 0x01D8
171#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_OFFSET 0x01DC
172#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_OFFSET 0x01E0
173#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_OFFSET 0x01E4
174#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_OFFSET 0x01E8
175#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_OFFSET 0x01EC
176#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_OFFSET 0x01F0
177#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_OFFSET 0x01F4
178#define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_OFFSET 0x01F8
179#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_OFFSET 0x01FC
180
181#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_OFFSET 0x0200
182#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_OFFSET 0x0204
183#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_OFFSET 0x0208
184#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_OFFSET 0x020C
185#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_OFFSET 0x0210
186#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_OFFSET 0x0214
187#define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_OFFSET 0x0218
188#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_OFFSET 0x021C
189#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_OFFSET 0x0220
190#define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_OFFSET 0x0224
191#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_OFFSET 0x0228
192
193#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_OFFSET 0x022C
194#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_OFFSET 0x0230
195#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_OFFSET 0x0234
196#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_OFFSET 0x0238
197#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_OFFSET 0x023C
198#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_OFFSET 0x0240
199#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_OFFSET 0x0244
200#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_OFFSET 0x0248
201#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_OFFSET 0x024C
202#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_OFFSET 0x0250
203#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_OFFSET 0x0254
204#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_OFFSET 0x0258
205#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_OFFSET 0x025C
206#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_OFFSET 0x0260
207#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_OFFSET 0x0264
208#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_OFFSET 0x0268
209
210#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_OFFSET 0x026C
211#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_OFFSET 0x0270
212#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_OFFSET 0x0274
213#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_OFFSET 0x0278
214#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_OFFSET 0x027C
215#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_OFFSET 0x0280
216#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_OFFSET 0x0284
217#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_OFFSET 0x0288
218
219#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_OFFSET 0x028C
220#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_OFFSET 0x0290
221#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_OFFSET 0x0294
222#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_OFFSET 0x0298
223#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_OFFSET 0x029C
224#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_OFFSET 0x02A0
225
226#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_OFFSET 0x02A4
227#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_OFFSET 0x02A8
228#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_OFFSET 0x02AC
229#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_OFFSET 0x02B0
230#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_OFFSET 0x02B4
231#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_OFFSET 0x02B8
232#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_OFFSET 0x02BC
233#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_OFFSET 0x02C0
234#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_OFFSET 0x02C4
235#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_OFFSET 0x02C8
236#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_OFFSET 0x02CC
237#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_OFFSET 0x02D0
238#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_OFFSET 0x02D4
239#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_OFFSET 0x02D8
240#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_OFFSET 0x02DC
241#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_OFFSET 0x02E0
242
243#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_OFFSET 0x02E4
244#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_OFFSET 0x02E8
245#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_OFFSET 0x02EC
246#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_OFFSET 0x02F0
247#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_OFFSET 0x02F4
248#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_OFFSET 0x02F8
249#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_OFFSET 0x02FC
250#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_OFFSET 0x0300
251#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_OFFSET 0x0304
252#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_OFFSET 0x0308
253#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_OFFSET 0x030C
254#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_OFFSET 0x0310
255#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_OFFSET 0x0314
256#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_OFFSET 0x0318
257#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_OFFSET 0x031C
258#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_OFFSET 0x0320
259
260#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_OFFSET 0x0324
261#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_OFFSET 0x0328
262#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_OFFSET 0x032C
263#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_OFFSET 0x0330
264#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_OFFSET 0x0334
265#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_OFFSET 0x0338
266#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_OFFSET 0x033C
267#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_OFFSET 0x0340
268#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_OFFSET 0x0344
269#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_OFFSET 0x0348
270#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_OFFSET 0x034C
271#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_OFFSET 0x0350
272#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_OFFSET 0x0354
273#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_OFFSET 0x0358
274#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_OFFSET 0x035C
275#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_OFFSET 0x0360
276#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_OFFSET 0x0364
277#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_OFFSET 0x0368
278#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_OFFSET 0x036C
279#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_OFFSET 0x0370
280#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_OFFSET 0x0374
281#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_OFFSET 0x0378
282#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_OFFSET 0x037C
283#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_OFFSET 0x0380
284#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_OFFSET 0x0384
285#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_OFFSET 0x0388
286#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_OFFSET 0x038C
287#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_OFFSET 0x0390
288#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_OFFSET 0x0394
289#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET 0x0398
290#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_0_X1 0
291#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4 BIT(0)
292#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_2_X2 BIT(1)
293#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_3_X6 (BIT(1) | BIT(0))
294#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_FAST 0
295#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_SLOW BIT(2)
296#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_DIS 0
297#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN BIT(3)
298#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_DIS 0
299#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN BIT(4)
300#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_0_100K_PD 0
301#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_1_5K_PU BIT(5)
302#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_2_47K_PU BIT(6)
303#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU (BIT(6) | BIT(5))
304
305#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET 0x039C
306#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_0_X1 0
307#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4 BIT(0)
308#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_2_X2 BIT(1)
309#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_3_X6 (BIT(1) | BIT(0))
310#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_FAST 0
311#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_SLOW BIT(2)
312#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_DIS 0
313#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN BIT(3)
314#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_DIS 0
315#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN BIT(4)
316#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_0_100K_PD 0
317#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_1_5K_PU BIT(5)
318#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_2_47K_PU BIT(6)
319#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU (BIT(6) | BIT(5))
320
321#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_OFFSET 0x03A0
322#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_OFFSET 0x03A4
323#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_OFFSET 0x03A8
324#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_OFFSET 0x03AC
325#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_OFFSET 0x03B0
326#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_OFFSET 0x03B4
327
328#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_OFFSET 0x03B8
329#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_OFFSET 0x03BC
330#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_OFFSET 0x03C0
331#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_OFFSET 0x03C4
332#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_OFFSET 0x03C8
333#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_OFFSET 0x03CC
334#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_OFFSET 0x03D0
335#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_OFFSET 0x03D4
336
337#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET 0x03D8
338#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_0_X1 0
339#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4 BIT(0)
340#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_2_X2 BIT(1)
341#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_3_X6 (BIT(1) | BIT(0))
342#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_FAST 0
343#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_SLOW BIT(2)
344#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_DIS 0
345#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN BIT(3)
346#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_DIS 0
347#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN BIT(4)
348#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_0_100K_PD 0
349#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_1_5K_PU BIT(5)
350#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_2_47K_PU BIT(6)
351#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU (BIT(6) | BIT(5))
352
353#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET 0x03DC
354#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_0_X1 0
355#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4 BIT(0)
356#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_2_X2 BIT(1)
357#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_3_X6 (BIT(1) | BIT(0))
358#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_FAST 0
359#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_SLOW BIT(2)
360#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_DIS 0
361#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN BIT(3)
362#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_DIS 0
363#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN BIT(4)
364#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_0_100K_PD 0
365#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_1_5K_PU BIT(5)
366#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_2_47K_PU BIT(6)
367#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU (BIT(6) | BIT(5))
368
369#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_OFFSET 0x03E0
370#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_OFFSET 0x03E4
371#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_OFFSET 0x03E8
372#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_OFFSET 0x03EC
373#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_OFFSET 0x03F0
374#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_OFFSET 0x03F4
375
376#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_OFFSET 0x03F8
377#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_OFFSET 0x03FC
378#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_OFFSET 0x0400
379#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_OFFSET 0x0404
380#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_OFFSET 0x0408
381#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_OFFSET 0x040C
382#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_OFFSET 0x0410
383#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_OFFSET 0x0414
384#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_OFFSET 0x0418
385#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_OFFSET 0x041C
386#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_OFFSET 0x0420
387#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_OFFSET 0x0424
388#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_OFFSET 0x0428
389#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_OFFSET 0x042C
390#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_OFFSET 0x0430
391#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_OFFSET 0x0434
392#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_OFFSET 0x0438
393#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_OFFSET 0x043C
394#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET 0x0440
395#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET 0x0444
396#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET 0x0448
397#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_OFFSET 0x044C
398#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_OFFSET 0x0450
399#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_OFFSET 0x0454
400#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_OFFSET 0x0458
401#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_OFFSET 0x045C
402#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_OFFSET 0x0460
403#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET 0x0464
404#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_OFFSET 0x0468
405#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_OFFSET 0x046C
406
407#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_OFFSET 0x0470
408#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_OFFSET 0x0474
409#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_OFFSET 0x0478
410#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_OFFSET 0x047C
411#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_OFFSET 0x0480
412#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_OFFSET 0x0484
413#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_OFFSET 0x0488
414#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_OFFSET 0x048C
415#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_OFFSET 0x0490
416#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_OFFSET 0x0494
417#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_OFFSET 0x0498
418
419#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_OFFSET 0x049C
420#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_OFFSET 0x04A0
421#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_OFFSET 0x04A4
422#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_OFFSET 0x04A8
423#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_OFFSET 0x04AC
424#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_OFFSET 0x04B0
425#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_OFFSET 0x04B4
426#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_OFFSET 0x04B8
427#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_OFFSET 0x04BC
428#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_OFFSET 0x04C0
429#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_OFFSET 0x04C4
430#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_OFFSET 0x04C8
431#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_OFFSET 0x04CC
432#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_OFFSET 0x04D0
433#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_OFFSET 0x04D4
434#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_OFFSET 0x04D8
435
436#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_OFFSET 0x04DC
437#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_OFFSET 0x04E0
438
439#define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_OFFSET 0x04E4
440#define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_OFFSET 0x04E8
441#define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_OFFSET 0x04EC
442#define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_OFFSET 0x04F0
443
444#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_OFFSET 0x04F4
445
446#define IOMUXC_CSI_DATA2_SELECT_INPUT_OFFSET 0x04F8
447#define IOMUXC_CSI_DATA3_SELECT_INPUT_OFFSET 0x04FC
448#define IOMUXC_CSI_DATA4_SELECT_INPUT_OFFSET 0x0500
449#define IOMUXC_CSI_DATA5_SELECT_INPUT_OFFSET 0x0504
450#define IOMUXC_CSI_DATA6_SELECT_INPUT_OFFSET 0x0508
451#define IOMUXC_CSI_DATA7_SELECT_INPUT_OFFSET 0x050C
452#define IOMUXC_CSI_DATA8_SELECT_INPUT_OFFSET 0x0510
453#define IOMUXC_CSI_DATA9_SELECT_INPUT_OFFSET 0x0514
454#define IOMUXC_CSI_HSYNC_SELECT_INPUT_OFFSET 0x0518
455#define IOMUXC_CSI_PIXCLK_SELECT_INPUT_OFFSET 0x051C
456#define IOMUXC_CSI_VSYNC_SELECT_INPUT_OFFSET 0x0520
457
458#define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_OFFSET 0x0524
459#define IOMUXC_ECSPI1_MISO_SELECT_INPUT_OFFSET 0x0528
460#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_OFFSET 0x052C
461#define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_OFFSET 0x0530
462#define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_OFFSET 0x0534
463#define IOMUXC_ECSPI2_MISO_SELECT_INPUT_OFFSET 0x0538
464#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_OFFSET 0x053C
465#define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_OFFSET 0x0540
466#define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_OFFSET 0x0544
467#define IOMUXC_ECSPI3_MISO_SELECT_INPUT_OFFSET 0x0548
468#define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_OFFSET 0x054C
469#define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_OFFSET 0x0550
470#define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_OFFSET 0x0554
471#define IOMUXC_ECSPI4_MISO_SELECT_INPUT_OFFSET 0x0558
472#define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_OFFSET 0x055C
473#define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_OFFSET 0x0560
474
475#define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_OFFSET 0x0564
476#define IOMUXC_ENET1_MDIO_SELECT_INPUT_OFFSET 0x0568
477#define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_OFFSET 0x056C
478#define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_OFFSET 0x0570
479#define IOMUXC_ENET2_MDIO_SELECT_INPUT_OFFSET 0x0574
480#define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_OFFSET 0x0578
481
482#define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_OFFSET 0x057C
483#define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_OFFSET 0x0580
484
485#define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_OFFSET 0x0584
486#define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_OFFSET 0x0588
487#define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_OFFSET 0x058C
488#define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_OFFSET 0x0590
489#define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_OFFSET 0x0594
490#define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_OFFSET 0x0598
491#define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_OFFSET 0x059C
492#define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_OFFSET 0x05A0
493#define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_OFFSET 0x05A4
494#define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_OFFSET 0x05A8
495#define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_OFFSET 0x05AC
496#define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_OFFSET 0x05B0
497#define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_OFFSET 0x05B4
498#define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_OFFSET 0x05B8
499#define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_OFFSET 0x05BC
500#define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_OFFSET 0x05C0
501#define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_OFFSET 0x05C4
502#define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_OFFSET 0x05C8
503#define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_OFFSET 0x05CC
504#define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_OFFSET 0x05D0
505
506#define IOMUXC_I2C1_SCL_SELECT_INPUT_OFFSET 0x05D4
507#define IOMUXC_I2C1_SDA_SELECT_INPUT_OFFSET 0x05D8
508#define IOMUXC_I2C2_SCL_SELECT_INPUT_OFFSET 0x05DC
509#define IOMUXC_I2C2_SDA_SELECT_INPUT_OFFSET 0x05E0
510#define IOMUXC_I2C3_SCL_SELECT_INPUT_OFFSET 0x05E4
511#define IOMUXC_I2C3_SDA_SELECT_INPUT_OFFSET 0x05E8
512#define IOMUXC_I2C4_SCL_SELECT_INPUT_OFFSET 0x05EC
513#define IOMUXC_I2C4_SDA_SELECT_INPUT_OFFSET 0x05F0
514
515#define IOMUXC_KPP_COL0_SELECT_INPUT_OFFSET 0x05F4
516#define IOMUXC_KPP_COL1_SELECT_INPUT_OFFSET 0x05F8
517#define IOMUXC_KPP_COL2_SELECT_INPUT_OFFSET 0x05FC
518#define IOMUXC_KPP_COL3_SELECT_INPUT_OFFSET 0x0600
519#define IOMUXC_KPP_COL4_SELECT_INPUT_OFFSET 0x0604
520#define IOMUXC_KPP_COL5_SELECT_INPUT_OFFSET 0x0608
521#define IOMUXC_KPP_COL6_SELECT_INPUT_OFFSET 0x060C
522#define IOMUXC_KPP_COL7_SELECT_INPUT_OFFSET 0x0610
523#define IOMUXC_KPP_ROW0_SELECT_INPUT_OFFSET 0x0614
524#define IOMUXC_KPP_ROW1_SELECT_INPUT_OFFSET 0x0618
525#define IOMUXC_KPP_ROW2_SELECT_INPUT_OFFSET 0x061C
526#define IOMUXC_KPP_ROW3_SELECT_INPUT_OFFSET 0x0620
527#define IOMUXC_KPP_ROW4_SELECT_INPUT_OFFSET 0x0624
528#define IOMUXC_KPP_ROW5_SELECT_INPUT_OFFSET 0x0628
529#define IOMUXC_KPP_ROW6_SELECT_INPUT_OFFSET 0x062C
530#define IOMUXC_KPP_ROW7_SELECT_INPUT_OFFSET 0x0630
531
532#define IOMUXC_LCD_BUSY_SELECT_INPUT_OFFSET 0x0634
533#define IOMUXC_LCD_DATA00_SELECT_INPUT_OFFSET 0x0638
534#define IOMUXC_LCD_DATA01_SELECT_INPUT_OFFSET 0x063C
535#define IOMUXC_LCD_DATA02_SELECT_INPUT_OFFSET 0x0640
536#define IOMUXC_LCD_DATA03_SELECT_INPUT_OFFSET 0x0644
537#define IOMUXC_LCD_DATA04_SELECT_INPUT_OFFSET 0x0648
538#define IOMUXC_LCD_DATA05_SELECT_INPUT_OFFSET 0x064C
539#define IOMUXC_LCD_DATA06_SELECT_INPUT_OFFSET 0x0650
540#define IOMUXC_LCD_DATA07_SELECT_INPUT_OFFSET 0x0654
541#define IOMUXC_LCD_DATA08_SELECT_INPUT_OFFSET 0x0658
542#define IOMUXC_LCD_DATA09_SELECT_INPUT_OFFSET 0x065C
543#define IOMUXC_LCD_DATA10_SELECT_INPUT_OFFSET 0x0660
544#define IOMUXC_LCD_DATA11_SELECT_INPUT_OFFSET 0x0664
545#define IOMUXC_LCD_DATA12_SELECT_INPUT_OFFSET 0x0668
546#define IOMUXC_LCD_DATA13_SELECT_INPUT_OFFSET 0x066C
547#define IOMUXC_LCD_DATA14_SELECT_INPUT_OFFSET 0x0670
548#define IOMUXC_LCD_DATA15_SELECT_INPUT_OFFSET 0x0674
549#define IOMUXC_LCD_DATA16_SELECT_INPUT_OFFSET 0x0678
550#define IOMUXC_LCD_DATA17_SELECT_INPUT_OFFSET 0x067C
551#define IOMUXC_LCD_DATA18_SELECT_INPUT_OFFSET 0x0680
552#define IOMUXC_LCD_DATA19_SELECT_INPUT_OFFSET 0x0684
553#define IOMUXC_LCD_DATA20_SELECT_INPUT_OFFSET 0x0688
554#define IOMUXC_LCD_DATA21_SELECT_INPUT_OFFSET 0x068C
555#define IOMUXC_LCD_DATA22_SELECT_INPUT_OFFSET 0x0690
556#define IOMUXC_LCD_DATA23_SELECT_INPUT_OFFSET 0x0694
557#define IOMUXC_LCD_VSYNC_SELECT_INPUT_OFFSET 0x0698
558
559#define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_OFFSET 0x069C
560#define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_OFFSET 0x06A0
561#define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_OFFSET 0x06A4
562#define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_OFFSET 0x06A8
563#define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_OFFSET 0x06AC
564#define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_OFFSET 0x06B0
565#define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_OFFSET 0x06B4
566#define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_OFFSET 0x06B8
567#define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_OFFSET 0x06BC
568#define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_OFFSET 0x06C0
569#define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_OFFSET 0x06C4
570#define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_OFFSET 0x06C8
571#define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_OFFSET 0x06CC
572#define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_OFFSET 0x06D0
573#define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_OFFSET 0x06D4
574#define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_OFFSET 0x06D8
575#define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_OFFSET 0x06DC
576
577#define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_OFFSET 0x06E0
578#define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_OFFSET 0x06E4
579#define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_OFFSET 0x06E8
580#define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_OFFSET 0x06EC
581
582#define IOMUXC_UART1_RTS_B_SELECT_INPUT_OFFSET 0x06F0
583#define IOMUXC_UART1_RX_DATA_SELECT_INPUT_OFFSET 0x06F4
584#define IOMUXC_UART2_RTS_B_SELECT_INPUT_OFFSET 0x06F8
585#define IOMUXC_UART2_RX_DATA_SELECT_INPUT_OFFSET 0x06FC
586#define IOMUXC_UART3_RTS_B_SELECT_INPUT_OFFSET 0x0700
587#define IOMUXC_UART3_RX_DATA_SELECT_INPUT_OFFSET 0x0704
588#define IOMUXC_UART4_RTS_B_SELECT_INPUT_OFFSET 0x0708
589#define IOMUXC_UART4_RX_DATA_SELECT_INPUT_OFFSET 0x070C
590#define IOMUXC_UART5_RTS_B_SELECT_INPUT_OFFSET 0x0710
591#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_OFFSET 0x0714
592#define IOMUXC_UART6_RTS_B_SELECT_INPUT_OFFSET 0x0718
593#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_OFFSET 0x071C
594#define IOMUXC_UART7_RTS_B_SELECT_INPUT_OFFSET 0x0720
595#define IOMUXC_UART7_RX_DATA_SELECT_INPUT_OFFSET 0x0724
596
597#define IOMUXC_USB_OTG2_OC_SELECT_INPUT_OFFSET 0x0728
598#define IOMUXC_USB_OTG1_OC_SELECT_INPUT_OFFSET 0x072C
599#define IOMUXC_USB_OTG2_ID_SELECT_INPUT_OFFSET 0x0730
600#define IOMUXC_USB_OTG1_ID_SELECT_INPUT_OFFSET 0x0734
601#define IOMUXC_SD3_CD_B_SELECT_INPUT_OFFSET 0x0738
602#define IOMUXC_SD3_WP_SELECT_INPUT_OFFSET 0x073C
603
604/* Pad mux/feature set routines */
605
606void imx_io_muxc_set_pad_alt_function(uint32_t pad_mux_offset, uint32_t alt_function);
607void imx_io_muxc_set_pad_features(uint32_t pad_feature_offset, uint32_t pad_features);
608
609#endif /* __IMX_IO_MUX_H__ */