blob: 3204ae74c82268b134d63c1be7e2f261c195338c [file] [log] [blame]
Caesar Wanga8456902016-10-27 01:12:34 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __SOC_ROCKCHIP_RK3399_DFS_H__
32#define __SOC_ROCKCHIP_RK3399_DFS_H__
33
34struct rk3399_sdram_default_config {
35 unsigned char bl;
36 /* 1:auto precharge, 0:never auto precharge */
37 unsigned char ap;
38 /* dram driver strength */
39 unsigned char dramds;
40 /* dram ODT, if odt=0, this parameter invalid */
41 unsigned char dramodt;
42 /* ca ODT, if odt=0, this parameter invalid
43 * only used by LPDDR4
44 */
45 unsigned char caodt;
46 unsigned char burst_ref_cnt;
47 /* zqcs period, unit(s) */
48 unsigned char zqcsi;
49};
50
Caesar Wanga8456902016-10-27 01:12:34 +080051struct drv_odt_lp_config {
Caesar Wanga8456902016-10-27 01:12:34 +080052 uint32_t pd_idle;
53 uint32_t sr_idle;
54 uint32_t sr_mc_gate_idle;
55 uint32_t srpd_lite_idle;
56 uint32_t standby_idle;
Derek Basehoreff461d02016-10-20 20:46:43 -070057 uint32_t odt_en;
Caesar Wanga8456902016-10-27 01:12:34 +080058
59 uint32_t dram_side_drv;
60 uint32_t dram_side_dq_odt;
61 uint32_t dram_side_ca_odt;
Caesar Wanga8456902016-10-27 01:12:34 +080062};
63
Caesar Wanga8456902016-10-27 01:12:34 +080064uint32_t ddr_set_rate(uint32_t hz);
65uint32_t ddr_round_rate(uint32_t hz);
66uint32_t ddr_get_rate(void);
Derek Basehoreff461d02016-10-20 20:46:43 -070067uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2);
68void dram_dfs_init(void);
Derek Basehoree13bc542017-02-24 14:31:36 +080069void ddr_prepare_for_sys_suspend(void);
70void ddr_prepare_for_sys_resume(void);
71
Caesar Wanga8456902016-10-27 01:12:34 +080072#endif