blob: 98cf63c8cd391e69da160ca2f5c5ab98707da7f9 [file] [log] [blame]
Samuel Hollandb8566642017-08-12 04:07:39 -05001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <platform.h>
9#include <platform_def.h>
10
11static unsigned char plat_power_domain_tree_desc[PLAT_MAX_PWR_LVL + 1] = {
12 /* One root node for the SoC */
13 1,
14 /* One node for each cluster */
15 PLATFORM_CLUSTER_COUNT,
16 /* One set of CPUs per cluster */
17 PLATFORM_MAX_CPUS_PER_CLUSTER,
18};
19
20int plat_core_pos_by_mpidr(u_register_t mpidr)
21{
22 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
23 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
24
25 if (MPIDR_AFFLVL3_VAL(mpidr) > 0 ||
26 MPIDR_AFFLVL2_VAL(mpidr) > 0 ||
27 cluster >= PLATFORM_CLUSTER_COUNT ||
28 core >= PLATFORM_MAX_CPUS_PER_CLUSTER) {
29 return -1;
30 }
31
32 return cluster * PLATFORM_MAX_CPUS_PER_CLUSTER + core;
33}
34
35const unsigned char *plat_get_power_domain_tree_desc(void)
36{
37 return plat_power_domain_tree_desc;
38}