| Manoj Kumar | 5887612 | 2021-01-10 16:12:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <common/debug.h> |
| 8 | #include <lib/utils.h> |
| 9 | #include <plat/arm/common/plat_arm.h> |
| 10 | |
| 11 | void bl2_platform_setup(void) |
| 12 | { |
| 13 | #ifdef TARGET_PLATFORM_SOC |
| 14 | /* |
| 15 | * Morello platform supports RDIMMs with ECC capability. To use the ECC |
| 16 | * capability, the entire DDR memory space has to be zeroed out before |
| 17 | * enabling the ECC bits in DMC-Bing. |
| 18 | * Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF during BL2 stage, |
| 19 | * as BL33 binary cannot be copied to DDR memory before enabling ECC. |
| 20 | * Rest of the DDR memory space is zeroed out during BL31 stage. |
| 21 | */ |
| 22 | INFO("Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF\n"); |
| 23 | zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE); |
| 24 | flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); |
| 25 | #endif |
| 26 | arm_bl2_platform_setup(); |
| 27 | } |