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Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +01001/*
Bipin Ravi86499742022-01-18 01:59:06 -06002 * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef NEOVERSE_N2_H
8#define NEOVERSE_N2_H
9
10/* Neoverse N2 ID register for revision r0p0 */
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -070011#define NEOVERSE_N2_MIDR U(0x410FD490)
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +010012
Bipin Ravi86499742022-01-18 01:59:06 -060013/* Neoverse N2 loop count for CVE-2022-23960 mitigation */
14#define NEOVERSE_N2_BHB_LOOP_COUNT U(32)
15
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +010016/*******************************************************************************
17 * CPU Power control register
18 ******************************************************************************/
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -070019#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
20#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +010021
22/*******************************************************************************
23 * CPU Extended Control register specific definitions.
24 ******************************************************************************/
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -070025#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
26#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
27#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +010028
29/*******************************************************************************
30 * CPU Auxiliary Control register specific definitions.
31 ******************************************************************************/
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -070032#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0
33#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
nayanpatel-arm2f153992021-10-06 15:31:24 -070034#define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
Bipin Ravieb35e852021-03-30 16:08:32 -050035
36/*******************************************************************************
37 * CPU Auxiliary Control register 2 specific definitions.
38 ******************************************************************************/
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -070039#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
40#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +010041
Bipin Ravi7e030692021-08-30 13:02:51 -050042/*******************************************************************************
43 * CPU Auxiliary Control register 5 specific definitions.
44 ******************************************************************************/
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -070045#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
46#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
nayanpatel-arm8e1aa012021-10-20 18:28:58 -070047#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
nayanpatel-armfed98132021-10-07 17:59:33 -070048#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -070049
50/*******************************************************************************
51 * CPU Auxiliary Control register specific definitions.
52 ******************************************************************************/
53#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5
54#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
55#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
56#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
Bipin Ravi7e030692021-08-30 13:02:51 -050057
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +010058#endif /* NEOVERSE_N2_H */