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git01.mediatek.com / filogic / atf / 1c2d89b41e99a161302e955cd4417fd268ee58ba / . / plat / xilinx / versal_net / include / plat_macros.S
blob: db7e42b35784e7ec392d07b67fd7463b5d6decae [file] [log] [blame]
Michal Simek91794362022-08-31 16:45:14 +0200[diff] [blame]1/*
Michal Simek2a47faa2023-04-14 08:43:51 +0200[diff] [blame]2 * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
Michal Simek91794362022-08-31 16:45:14 +0200[diff] [blame]3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
Jay Buddhabhatti6a44ad02023-02-28 01:23:04 -0800[diff] [blame]4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Michal Simek91794362022-08-31 16:45:14 +0200[diff] [blame]5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef PLAT_MACROS_S
10#define PLAT_MACROS_S
11
12#include <drivers/arm/gic_common.h>
13#include <drivers/arm/gicv2.h>
14#include <drivers/arm/gicv3.h>
15
16#include "../include/platform_def.h"
17
18.section .rodata.gic_reg_name, "aS"
19/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
20gicc_regs:
21 .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
22
23/* Applicable only to GICv3 with SRE enabled */
24icc_regs:
25 .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
26
27/* Registers common to both GICv2 and GICv3 */
28gicd_pend_reg:
29 .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
30newline:
31 .asciz "\n"
32spacer:
33 .asciz ":\t\t0x"
34
35 /* ---------------------------------------------
36 * The below utility macro prints out relevant GIC
37 * registers whenever an unhandled exception is
38 * taken in BL31 on Versal NET platform.
39 * Expects: GICD base in x16, GICC base in x17
40 * Clobbers: x0 - x10, sp
41 * ---------------------------------------------
42 */
43 .macro versal_net_print_gic_regs
44 /* Check for GICv3 system register access */
45 mrs x7, id_aa64pfr0_el1
46 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
47 cmp x7, #1
48 b.ne print_gicv2
49
50 /* Check for SRE enable */
51 mrs x8, ICC_SRE_EL3
52 tst x8, #ICC_SRE_SRE_BIT
53 b.eq print_gicv2
54
55 /* Load the icc reg list to x6 */
56 adr x6, icc_regs
57 /* Load the icc regs to gp regs used by str_in_crash_buf_print */
58 mrs x8, ICC_HPPIR0_EL1
59 mrs x9, ICC_HPPIR1_EL1
60 mrs x10, ICC_CTLR_EL3
61 /* Store to the crash buf and print to console */
62 bl str_in_crash_buf_print
63 b print_gic_common
64
65print_gicv2:
66 /* Load the gicc reg list to x6 */
67 adr x6, gicc_regs
68 /* Load the gicc regs to gp regs used by str_in_crash_buf_print */
69 ldr w8, [x17, #GICC_HPPIR]
70 ldr w9, [x17, #GICC_AHPPIR]
71 ldr w10, [x17, #GICC_CTLR]
72 /* Store to the crash buf and print to console */
73 bl str_in_crash_buf_print
74
75print_gic_common:
76 /* Print the GICD_ISPENDR regs */
77 add x7, x16, #GICD_ISPENDR
78 adr x4, gicd_pend_reg
79 bl asm_print_str
80gicd_ispendr_loop:
81 sub x4, x7, x16
82 cmp x4, #0x280
83 b.eq exit_print_gic_regs
84 bl asm_print_hex
85
86 adr x4, spacer
87 bl asm_print_str
88
89 ldr x4, [x7], #8
90 bl asm_print_hex
91
92 adr x4, newline
93 bl asm_print_str
94 b gicd_ispendr_loop
95exit_print_gic_regs:
96 .endm
97
98 /* ---------------------------------------------
99 * The below required platform porting macro
100 * prints out relevant GIC and CCI registers
101 * whenever an unhandled exception is taken in
102 * BL31.
103 * Clobbers: x0 - x10, x16, x17, sp
104 * ---------------------------------------------
105 */
106 .macro plat_crash_print_regs
107 /*
108 * Empty for now to handle more platforms variant.
109 * Uncomment it when versions are stable
110 */
111 /*
Jay Buddhabhatti6a44ad02023-02-28 01:23:04 -0800[diff] [blame]112 mov_imm x17, PLAT_GICD_BASE_VALUE
113 mov_imm x16, PLAT_GICR_BASE_VALUE
Michal Simek91794362022-08-31 16:45:14 +0200[diff] [blame]114 versal_net_print_gic_regs
115 */
116 .endm
117
118#endif /* PLAT_MACROS_S */