Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
| 8 | #include <assert.h> |
| 9 | #include <bl31/bl31.h> |
| 10 | #include <common/bl_common.h> |
| 11 | #include <common/interrupt_props.h> |
| 12 | #include <drivers/console.h> |
| 13 | #include <context.h> |
| 14 | #include <lib/el3_runtime/context_mgmt.h> |
| 15 | #include <cortex_a57.h> |
| 16 | #include <common/debug.h> |
| 17 | #include <denver.h> |
| 18 | #include <drivers/arm/gic_common.h> |
| 19 | #include <drivers/arm/gicv2.h> |
| 20 | #include <bl31/interrupt_mgmt.h> |
| 21 | #include <mce.h> |
| 22 | #include <plat/common/platform.h> |
| 23 | #include <tegra_def.h> |
| 24 | #include <tegra_platform.h> |
| 25 | #include <tegra_private.h> |
| 26 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 27 | |
| 28 | DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) |
| 29 | extern uint64_t tegra_enable_l2_ecc_parity_prot; |
| 30 | |
| 31 | /******************************************************************************* |
| 32 | * The Tegra power domain tree has a single system level power domain i.e. a |
| 33 | * single root node. The first entry in the power domain descriptor specifies |
| 34 | * the number of power domains at the highest power level. |
| 35 | ******************************************************************************* |
| 36 | */ |
| 37 | const unsigned char tegra_power_domain_tree_desc[] = { |
| 38 | /* No of root nodes */ |
| 39 | 1, |
| 40 | /* No of clusters */ |
| 41 | PLATFORM_CLUSTER_COUNT, |
| 42 | /* No of CPU cores - cluster0 */ |
| 43 | PLATFORM_MAX_CPUS_PER_CLUSTER, |
| 44 | /* No of CPU cores - cluster1 */ |
| 45 | PLATFORM_MAX_CPUS_PER_CLUSTER |
| 46 | }; |
| 47 | |
| 48 | /* |
| 49 | * Table of regions to map using the MMU. |
| 50 | */ |
| 51 | static const mmap_region_t tegra_mmap[] = { |
| 52 | MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ |
| 53 | MT_DEVICE | MT_RW | MT_SECURE), |
| 54 | MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ |
| 55 | MT_DEVICE | MT_RW | MT_SECURE), |
| 56 | MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ |
| 57 | MT_DEVICE | MT_RW | MT_SECURE), |
| 58 | MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ |
| 59 | MT_DEVICE | MT_RW | MT_SECURE), |
| 60 | MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ |
| 61 | MT_DEVICE | MT_RW | MT_SECURE), |
| 62 | MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ |
| 63 | MT_DEVICE | MT_RW | MT_SECURE), |
| 64 | MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ |
| 65 | MT_DEVICE | MT_RW | MT_SECURE), |
| 66 | MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ |
| 67 | MT_DEVICE | MT_RW | MT_SECURE), |
| 68 | MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ |
| 69 | MT_DEVICE | MT_RW | MT_SECURE), |
| 70 | MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ |
| 71 | MT_DEVICE | MT_RW | MT_SECURE), |
| 72 | MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ |
| 73 | MT_DEVICE | MT_RW | MT_SECURE), |
| 74 | MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ |
| 75 | MT_DEVICE | MT_RW | MT_SECURE), |
| 76 | MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ |
| 77 | MT_DEVICE | MT_RW | MT_SECURE), |
| 78 | MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ |
| 79 | MT_DEVICE | MT_RW | MT_SECURE), |
| 80 | MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ |
| 81 | MT_DEVICE | MT_RW | MT_SECURE), |
| 82 | MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ |
| 83 | MT_DEVICE | MT_RW | MT_SECURE), |
Pritesh Raithatha | 1c2b5c7 | 2017-01-24 14:16:07 +0530 | [diff] [blame^] | 84 | MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ |
| 85 | MT_DEVICE | MT_RW | MT_SECURE), |
| 86 | MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */ |
| 87 | MT_DEVICE | MT_RW | MT_SECURE), |
| 88 | MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */ |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 89 | MT_DEVICE | MT_RW | MT_SECURE), |
| 90 | {0} |
| 91 | }; |
| 92 | |
| 93 | /******************************************************************************* |
| 94 | * Set up the pagetables as per the platform memory map & initialize the MMU |
| 95 | ******************************************************************************/ |
| 96 | const mmap_region_t *plat_get_mmio_map(void) |
| 97 | { |
| 98 | /* MMIO space */ |
| 99 | return tegra_mmap; |
| 100 | } |
| 101 | |
| 102 | /******************************************************************************* |
| 103 | * Handler to get the System Counter Frequency |
| 104 | ******************************************************************************/ |
| 105 | unsigned int plat_get_syscnt_freq2(void) |
| 106 | { |
| 107 | return 31250000; |
| 108 | } |
| 109 | |
| 110 | /******************************************************************************* |
| 111 | * Maximum supported UART controllers |
| 112 | ******************************************************************************/ |
| 113 | #define TEGRA186_MAX_UART_PORTS 7 |
| 114 | |
| 115 | /******************************************************************************* |
| 116 | * This variable holds the UART port base addresses |
| 117 | ******************************************************************************/ |
| 118 | static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { |
| 119 | 0, /* undefined - treated as an error case */ |
| 120 | TEGRA_UARTA_BASE, |
| 121 | TEGRA_UARTB_BASE, |
| 122 | TEGRA_UARTC_BASE, |
| 123 | TEGRA_UARTD_BASE, |
| 124 | TEGRA_UARTE_BASE, |
| 125 | TEGRA_UARTF_BASE, |
| 126 | TEGRA_UARTG_BASE, |
| 127 | }; |
| 128 | |
| 129 | /******************************************************************************* |
| 130 | * Retrieve the UART controller base to be used as the console |
| 131 | ******************************************************************************/ |
| 132 | uint32_t plat_get_console_from_id(int id) |
| 133 | { |
| 134 | if (id > TEGRA186_MAX_UART_PORTS) |
| 135 | return 0; |
| 136 | |
| 137 | return tegra186_uart_addresses[id]; |
| 138 | } |
| 139 | |
| 140 | /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ |
| 141 | #define TEGRA186_VER_A02P 0x1201 |
| 142 | |
| 143 | /******************************************************************************* |
| 144 | * Handler for early platform setup |
| 145 | ******************************************************************************/ |
| 146 | void plat_early_platform_setup(void) |
| 147 | { |
| 148 | int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
| 149 | uint32_t chip_subrev, val; |
| 150 | |
| 151 | /* sanity check MCE firmware compatibility */ |
| 152 | mce_verify_firmware_version(); |
| 153 | |
| 154 | /* |
| 155 | * Enable ECC and Parity Protection for Cortex-A57 CPUs |
| 156 | * for Tegra A02p SKUs |
| 157 | */ |
| 158 | if (impl != DENVER_IMPL) { |
| 159 | |
| 160 | /* get the major, minor and sub-version values */ |
| 161 | chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & |
| 162 | SUBREVISION_MASK; |
| 163 | |
| 164 | /* prepare chip version number */ |
| 165 | val = (tegra_get_chipid_major() << 12) | |
| 166 | (tegra_get_chipid_minor() << 8) | |
| 167 | chip_subrev; |
| 168 | |
| 169 | /* enable L2 ECC for Tegra186 A02P and beyond */ |
| 170 | if (val >= TEGRA186_VER_A02P) { |
| 171 | |
| 172 | val = read_l2ctlr_el1(); |
| 173 | val |= L2_ECC_PARITY_PROTECTION_BIT; |
| 174 | write_l2ctlr_el1(val); |
| 175 | |
| 176 | /* |
| 177 | * Set the flag to enable ECC/Parity Protection |
| 178 | * when we exit System Suspend or Cluster Powerdn |
| 179 | */ |
| 180 | tegra_enable_l2_ecc_parity_prot = 1; |
| 181 | } |
| 182 | } |
| 183 | } |
| 184 | |
| 185 | /* Secure IRQs for Tegra186 */ |
| 186 | static const irq_sec_cfg_t tegra186_sec_irqs[] = { |
| 187 | [0] = { |
| 188 | TEGRA186_BPMP_WDT_IRQ, |
| 189 | TEGRA186_SEC_IRQ_TARGET_MASK, |
| 190 | INTR_TYPE_EL3, |
| 191 | }, |
| 192 | [1] = { |
| 193 | TEGRA186_BPMP_WDT_IRQ, |
| 194 | TEGRA186_SEC_IRQ_TARGET_MASK, |
| 195 | INTR_TYPE_EL3, |
| 196 | }, |
| 197 | [2] = { |
| 198 | TEGRA186_SPE_WDT_IRQ, |
| 199 | TEGRA186_SEC_IRQ_TARGET_MASK, |
| 200 | INTR_TYPE_EL3, |
| 201 | }, |
| 202 | [3] = { |
| 203 | TEGRA186_SCE_WDT_IRQ, |
| 204 | TEGRA186_SEC_IRQ_TARGET_MASK, |
| 205 | INTR_TYPE_EL3, |
| 206 | }, |
| 207 | [4] = { |
| 208 | TEGRA186_TOP_WDT_IRQ, |
| 209 | TEGRA186_SEC_IRQ_TARGET_MASK, |
| 210 | INTR_TYPE_EL3, |
| 211 | }, |
| 212 | [5] = { |
| 213 | TEGRA186_AON_WDT_IRQ, |
| 214 | TEGRA186_SEC_IRQ_TARGET_MASK, |
| 215 | INTR_TYPE_EL3, |
| 216 | }, |
| 217 | }; |
| 218 | |
| 219 | /******************************************************************************* |
| 220 | * Initialize the GIC and SGIs |
| 221 | ******************************************************************************/ |
| 222 | void plat_gic_setup(void) |
| 223 | { |
| 224 | tegra_gic_setup(tegra186_sec_irqs, |
| 225 | sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); |
| 226 | |
| 227 | /* |
| 228 | * Initialize the FIQ handler only if the platform supports any |
| 229 | * FIQ interrupt sources. |
| 230 | */ |
| 231 | if (sizeof(tegra186_sec_irqs) > 0) |
| 232 | tegra_fiq_handler_setup(); |
| 233 | } |
| 234 | |
| 235 | /******************************************************************************* |
| 236 | * Return pointer to the BL31 params from previous bootloader |
| 237 | ******************************************************************************/ |
| 238 | struct tegra_bl31_params *plat_get_bl31_params(void) |
| 239 | { |
| 240 | uint32_t val; |
| 241 | |
| 242 | val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); |
| 243 | |
| 244 | return (struct tegra_bl31_params *)(uintptr_t)val; |
| 245 | } |
| 246 | |
| 247 | /******************************************************************************* |
| 248 | * Return pointer to the BL31 platform params from previous bootloader |
| 249 | ******************************************************************************/ |
| 250 | plat_params_from_bl2_t *plat_get_bl31_plat_params(void) |
| 251 | { |
| 252 | uint32_t val; |
| 253 | |
| 254 | val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); |
| 255 | |
| 256 | return (plat_params_from_bl2_t *)(uintptr_t)val; |
| 257 | } |