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Soby Mathew748be1d2016-05-05 14:10:46 +01001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#include <aem_generic.h>
31#include <arch.h>
32#include <asm_macros.S>
33#include <assert_macros.S>
34#include <cpu_macros.S>
35
36func aem_generic_core_pwr_dwn
37 /* Assert if cache is enabled */
38#if ASM_ASSERTION
39 ldcopr r0, SCTLR
40 tst r0, #SCTLR_C_BIT
41 ASM_ASSERT(eq)
42#endif
43 /* ---------------------------------------------
44 * Flush L1 cache to PoU.
45 * ---------------------------------------------
46 */
47 mov r0, #DC_OP_CISW
48 b dcsw_op_louis
49endfunc aem_generic_core_pwr_dwn
50
51
52func aem_generic_cluster_pwr_dwn
53 /* Assert if cache is enabled */
54#if ASM_ASSERTION
55 ldcopr r0, SCTLR
56 tst r0, #SCTLR_C_BIT
57 ASM_ASSERT(eq)
58#endif
59 /* ---------------------------------------------
60 * Flush L1 and L2 caches to PoC.
61 * ---------------------------------------------
62 */
63 mov r0, #DC_OP_CISW
64 b dcsw_op_all
65endfunc aem_generic_cluster_pwr_dwn
66
67/* cpu_ops for Base AEM FVP */
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +000068declare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \
69 aem_generic_core_pwr_dwn, \
70 aem_generic_cluster_pwr_dwn