Antonio Nino Diaz | 272e871 | 2018-09-18 01:36:00 +0100 | [diff] [blame] | 1 | /* |
Carlo Caione | 1afdfb0 | 2019-08-24 18:47:06 +0100 | [diff] [blame^] | 2 | * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. |
Antonio Nino Diaz | 272e871 | 2018-09-18 01:36:00 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <arch.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <lib/utils_def.h> |
Antonio Nino Diaz | 272e871 | 2018-09-18 01:36:00 +0100 | [diff] [blame] | 12 | |
| 13 | #include "../gxbb_def.h" |
| 14 | |
| 15 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 16 | #define PLATFORM_LINKER_ARCH aarch64 |
| 17 | |
| 18 | /* Special value used to verify platform parameters from BL2 to BL31 */ |
| 19 | #define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) |
| 20 | |
| 21 | #define PLATFORM_STACK_SIZE UL(0x1000) |
| 22 | |
| 23 | #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) |
| 24 | #define PLATFORM_CLUSTER_COUNT U(1) |
| 25 | #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER |
| 26 | #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT |
| 27 | |
Carlo Caione | 1afdfb0 | 2019-08-24 18:47:06 +0100 | [diff] [blame^] | 28 | #define AML_PRIMARY_CPU U(0) |
Antonio Nino Diaz | 272e871 | 2018-09-18 01:36:00 +0100 | [diff] [blame] | 29 | |
| 30 | #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 |
| 31 | #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ |
| 32 | PLATFORM_CORE_COUNT) |
| 33 | |
| 34 | #define PLAT_MAX_RET_STATE U(1) |
| 35 | #define PLAT_MAX_OFF_STATE U(2) |
| 36 | |
| 37 | /* Local power state for power domains in Run state. */ |
| 38 | #define PLAT_LOCAL_STATE_RUN U(0) |
| 39 | /* Local power state for retention. Valid only for CPU power domains */ |
| 40 | #define PLAT_LOCAL_STATE_RET U(1) |
| 41 | /* Local power state for power-down. Valid for CPU and cluster power domains. */ |
| 42 | #define PLAT_LOCAL_STATE_OFF U(2) |
| 43 | |
| 44 | /* |
| 45 | * Macros used to parse state information from State-ID if it is using the |
| 46 | * recommended encoding for State-ID. |
| 47 | */ |
| 48 | #define PLAT_LOCAL_PSTATE_WIDTH U(4) |
| 49 | #define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) |
| 50 | |
| 51 | /* |
| 52 | * Some data must be aligned on the biggest cache line size in the platform. |
| 53 | * This is known only to the platform as it might have a combination of |
| 54 | * integrated and external caches. |
| 55 | */ |
| 56 | #define CACHE_WRITEBACK_SHIFT U(6) |
| 57 | #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) |
| 58 | |
| 59 | /* Memory-related defines */ |
| 60 | #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) |
| 61 | #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) |
| 62 | |
| 63 | #define MAX_MMAP_REGIONS 12 |
| 64 | #define MAX_XLAT_TABLES 5 |
| 65 | |
| 66 | #endif /* PLATFORM_DEF_H */ |