David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 1 | /* |
Dimitris Papastamos | 1be747f | 2018-02-14 10:28:36 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __CORTEX_A75_H__ |
| 8 | #define __CORTEX_A75_H__ |
| 9 | |
| 10 | /* Cortex-A75 MIDR */ |
| 11 | #define CORTEX_A75_MIDR 0x410fd0a0 |
| 12 | |
| 13 | /******************************************************************************* |
| 14 | * CPU Extended Control register specific definitions. |
| 15 | ******************************************************************************/ |
| 16 | #define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 17 | #define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 18 | |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 19 | /******************************************************************************* |
| 20 | * CPU Auxiliary Control register specific definitions. |
| 21 | ******************************************************************************/ |
| 22 | #define CORTEX_A75_CPUACTLR_EL1 S3_0_C15_C1_0 |
| 23 | |
| 24 | #define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (1 << 35) |
| 25 | |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 26 | /* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ |
| 27 | #define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1 |
| 28 | |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 29 | #define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4) |
| 30 | |
| 31 | /* |
| 32 | * The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are |
| 33 | * fixed and are enabled (Group 0). Events 3 and 4 (Group 1) are |
| 34 | * programmable by programming the appropriate Event count bits in |
| 35 | * CPUAMEVTYPER<n> register and are disabled by default. Platforms may |
| 36 | * enable this with suitable programming. |
| 37 | */ |
Dimitris Papastamos | 864364a | 2018-02-27 10:55:39 +0000 | [diff] [blame] | 38 | #define CORTEX_A75_AMU_NR_COUNTERS U(5) |
| 39 | #define CORTEX_A75_AMU_GROUP0_MASK U(0x7) |
| 40 | #define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3) |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 41 | |
Dimitris Papastamos | d7e2e9e | 2017-12-11 11:45:35 +0000 | [diff] [blame] | 42 | #ifndef __ASSEMBLY__ |
| 43 | #include <stdint.h> |
| 44 | |
| 45 | uint64_t cortex_a75_amu_cnt_read(int idx); |
| 46 | void cortex_a75_amu_cnt_write(int idx, uint64_t val); |
| 47 | unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void); |
| 48 | unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void); |
| 49 | void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask); |
| 50 | void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask); |
| 51 | #endif /* __ASSEMBLY__ */ |
| 52 | |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 53 | #endif /* __CORTEX_A75_H__ */ |